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| amd-k6- iii processor data sheet ?
trademarks amd, the amd logo, k6, 3dnow!, and combinations thereof, k86, and super7 are trademarks, and amd-k6 and risc86 are registered trademarks of advanced micro devices, inc. microsoft, windows, and windows nt are registered trademarks of microsoft corporation. netware is a registered trademark of novell, inc. mmx is a trademark of intel corporation. the tap state diagram is reprinted from ieee std 1149.1-1990 ieee standard test access port and boundary-scan architecture, copyright ? 1990 by the institute of electrical and electronics engineers, inc. the ieee disclaims any responsibility or liability resulting from the placement and use in the described manner. information is reprinted with the permission of the ieee. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. contents iii 21918b/0october 1999 amd-k6 ? - iii processor data sheet contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii 1 amd-k6 ? -iii processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 super7? platform initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 super7? platform enhancements. . . . . . . . . . . . . . . . . . . . . . . 3 super7? platform advantages . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 amd-k6 ? - iii processor microarchitecture overview . . . . . . 5 enhanced risc86 ? microarchitecture . . . . . . . . . . . . . . . . . . . 6 2.3 cache, instruction prefetch, and predecode bits . . . . . . . . . . 9 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . . . . 11 instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 instruction decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register x and y pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 branch-prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 branch history table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 branch target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 return address stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 branch execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 integer data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 segment registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 instruction pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 floating-point registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 floating-point register data types . . . . . . . . . . . . . . . . . . . . . 28 mmx?/3dnow!? registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mmx? data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3dnow!? data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 debug registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 iv contents amd-k6 ? - iii processor data sheet 21918b/0october 1999 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . . 37 memory management registers . . . . . . . . . . . . . . . . . . . . . . . 45 task state segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2 instructions supported by the amd-k6 ? - iii processor . . . . 54 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1 signal terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2 a20m# (address bit 20 mask) . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.3 a[31:3] (address bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.4 ads# (address strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.5 adsc# (address strobe copy) . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6 ahold (address hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.7 ap (address parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.8 apchk# (address parity check) . . . . . . . . . . . . . . . . . . . . . . 90 4.9 be[7:0]# (byte enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.10 bf[2:0] (bus frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.11 boff# (backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.12 brdy# (burst ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.13 brdyc# (burst ready copy) . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.14 breq (bus request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.15 cache# (cacheable access) . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.16 clk (clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.17 d/c# (data/code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.18 d[63:0] (data bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.19 dp[7:0] (data parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.20 eads# (external address strobe) . . . . . . . . . . . . . . . . . . . . 100 4.21 ewbe# (external write buffer empty) . . . . . . . . . . . . . . . . 101 4.22 ferr# (floating-point error) . . . . . . . . . . . . . . . . . . . . . . . 102 4.23 flush# (cache flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.24 hit# (inquire cycle hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.25 hitm# (inquire cycle hit to modified line) . . . . . . . . . . . 104 4.26 hlda (hold acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.27 hold (bus hold request) . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.28 ignne# (ignore numeric exception) . . . . . . . . . . . . . . . . . 106 4.29 init (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.30 intr (maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.31 inv (invalidation request) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.32 ken# (cache enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.33 lock# (bus lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.34 m/io# (memory or i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.35 na# (next address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.36 nmi (non-maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . 112 4.37 pcd (page cache disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.38 pchk# (parity check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 contents v 21918b/0october 1999 amd-k6 ? - iii processor data sheet 4.39 pwt (page writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.40 reset (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.41 rsvd (reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.42 scyc (split cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.43 smi# (system management interrupt) . . . . . . . . . . . . . . . . 117 4.44 smiact# (system management interrupt active) . . . . . . 118 4.45 stpclk# (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.46 tck (test clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.47 tdi (test data input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.48 tdo (test data output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.49 tms (test mode select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.50 trst# (test reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.51 vcc2det (vcc2 detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.52 vcc2h/l# (vcc2 high/low) . . . . . . . . . . . . . . . . . . . . . . . . 121 4.53 w/r# (write/read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.54 wb/wt# (writeback or writethrough) . . . . . . . . . . . . . . . . 123 5 bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.2 bus state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . 129 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 data-na# requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.3 memory reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . 132 single-transfer memory read and write . . . . . . . . . . . . . . . 132 misaligned single-transfer memory read and write . . . . . 134 burst reads and pipelined burst reads . . . . . . . . . . . . . . . . 136 burst writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.4 i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 basic i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 misaligned i/o read and write . . . . . . . . . . . . . . . . . . . . . . . 141 5.5 inquire and bus arbitration cycles . . . . . . . . . . . . . . . . . . . 142 hold and hold acknowledge cycle . . . . . . . . . . . . . . . . . . . . 142 hold-initiated inquire hit to shared or exclusive line . . 144 hold-initiated inquire hit to modified line . . . . . . . . . . . 146 ahold-initiated inquire miss. . . . . . . . . . . . . . . . . . . . . . . . 148 ahold-initiated inquire hit to shared or exclusive line. 150 ahold-initiated inquire hit to modified line . . . . . . . . . . 152 ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 bus backoff (boff#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 locked cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 basic locked operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 locked operation with boff# intervention . . . . . . . . . . . . 160 vi contents amd-k6 ? - iii processor data sheet 21918b/0october 1999 interrupt acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.6 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 basic special bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 stop grant and stop clock states . . . . . . . . . . . . . . . . . . . . . 167 init-initiated transition from protected mode to real mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6 power-on configuration and initialization . . . . . . . . . . . . . . 173 6.1 signals sampled during the falling transition of reset 173 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.2 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.3 state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 174 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.4 state of processor after init . . . . . . . . . . . . . . . . . . . . . . . . 177 7 cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.1 mesi states in the l1 data cache and l2 cache . . . . . . . . 181 7.2 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.3 cache operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 cache-related signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.4 cache disabling and flushing . . . . . . . . . . . . . . . . . . . . . . . 185 l1 and l2 cache disabling. . . . . . . . . . . . . . . . . . . . . . . . . . . 185 l2 cache disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.5 l2 cache and tag array testing . . . . . . . . . . . . . . . . . . . . . 186 7.6 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.7 cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.8 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 write to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 write allocate limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 write allocate logic mechanisms and conditions . . . . . . . 192 7.9 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 hardware prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 software prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.10 cache states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.11 cache coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 internal snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 pfir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 wbinvd and invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 cache-line replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.12 writethrough versus writeback coherency states . . . . . . . 202 contents vii 21918b/0october 1999 amd-k6 ? - iii processor data sheet 7.13 a20m# masking of cache accesses . . . . . . . . . . . . . . . . . . . 202 8 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.1 ewbe control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.2 memory type range registers . . . . . . . . . . . . . . . . . . . . . . . 205 uc/wc cacheability control register (uwccr) . . . . . . . . 205 9 floating-point and multimedia execution units . . . . . . . . . 209 9.1 floating-point execution unit . . . . . . . . . . . . . . . . . . . . . . . 209 handling floating-point exceptions . . . . . . . . . . . . . . . . . . . 209 external logic support of floating-point exceptions . . . . . 209 9.2 multimedia and 3dnow!? execution units . . . . . . . . . . . . 211 9.3 floating-point and mmx?/3dnow!? instruction compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 ferr# and ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 10 system management mode (smm) . . . . . . . . . . . . . . . . . . . . 213 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.2 smm operating mode and default register values . . . . . 213 10.3 smm state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 10.4 smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 10.5 smm base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.6 halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.7 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 10.8 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 10.9 exceptions, interrupts, and debug in smm . . . . . . . . . . . . 222 11 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11.1 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11.2 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 11.3 boundary-scan test access port (tap) . . . . . . . . . . . . . . . . 225 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 tap signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . 232 11.4 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 11.5 l2 cache and tag array testing . . . . . . . . . . . . . . . . . . . . . 237 level-2 cache array access register (l2aar) . . . . . . . . . . 237 11.6 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 debug registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 viii contents amd-k6 ? - iii processor data sheet 21918b/0october 1999 debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 12.1 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 enter halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 exit halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 12.2 stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 enter stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 exit stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 12.3 stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 enter stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . 252 exit stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . 252 12.4 stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 enter stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 exit stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 13 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.1 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 13.2 decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . 256 13.3 pin connection requirements . . . . . . . . . . . . . . . . . . . . . . . 257 14 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.2 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 14.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 15 i/o buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.1 i/o buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 15.2 i/o model application note . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.3 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 265 16 signal switching characteristics . . . . . . . . . . . . . . . . . . . . . . 267 16.1 clk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 267 16.2 clock switching characteristics for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.3 clock switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 16.4 valid delay, float, setup, and hold timings . . . . . . . . . . . 269 16.5 output delay timings for 100-mhz bus operation . . . . . . 270 16.6 input setup and hold timings for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 16.7 output delay timings for 66-mhz bus operation . . . . . . . 274 16.8 input setup and hold timings for 66-mhz bus operation 276 contents ix 21918b/0october 1999 amd-k6 ? - iii processor data sheet 16.9 reset and test signal timing . . . . . . . . . . . . . . . . . . . . . . 278 17 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 17.1 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . 285 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 measuring case temperature . . . . . . . . . . . . . . . . . . . . . . . . 288 17.2 layout and airflow considerations . . . . . . . . . . . . . . . . . . . 288 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 airflow management in a system design . . . . . . . . . . . . . . . 290 18 pin description diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 19 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 20 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.1 321-pin staggered cpga package specification . . . . . . . . 297 21 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 x contents amd-k6 ? - iii processor data sheet 21918b/0october 1999 list of figures xi 21918b/0october 1999 amd-k6 ? - iii processor data sheet list of figures figure 1. amd-k6 ? - iii processor block diagram . . . . . . . . . . . . . . . . . . . . 7 figure 2. cache sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. the instruction buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. amd-k6 ? - iii processor decode logic . . . . . . . . . . . . . . . . . . . . 12 figure 5. amd-k6 ? - iii processor scheduler . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. register x and y functional units . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. eax register with 16-bit and 8-bit name components. . . . . . 22 figure 8. integer data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. fpu status word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. fpu control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. fpu tag word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. packed decimal data register . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16. precision real data registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 17. mmx?/3dnow!? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 18. mmx? data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. 3dnow!? data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20. eflags registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. control register 3 (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23. control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 24. control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 25. control register 0 (cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 26. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 27. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 28. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 29. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . . 36 figure 30. machine-check address register (mcar) . . . . . . . . . . . . . . . . 38 figure 31. machine-check type register (mctr) . . . . . . . . . . . . . . . . . . . 38 figure 32. test register 12 (tr12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 33. time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 34. extended feature enable register (efer) msr c000_0080h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 35. syscall/sysret target address register (star) . . . . . . . 40 xii list of figures amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 36. write handling control register (whcr) msr c0000_0082h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 37. uc/wc cacheability control register (uwccr) msr c0000_0085h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 38. processor state observability register (psor) msr c000_0087h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 39. page flush/invalidate register (pfir) msr c000_0088h . . 42 figure 40. l2 tag or data location - edx . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 41. l2 data - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 42. l2 tag information - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 43. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 44. task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 45. 4-kbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 46. 4-mbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 47. page directory entry 4-kbyte page table (pde) . . . . . . . . . . . 49 figure 48. page directory entry 4-mbyte page table (pde) . . . . . . . . . . 49 figure 49. page table entry (pte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 50. application segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 51. system segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 52. gate descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 53. logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 54. waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 55. bus state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 56. non-pipelined single-transfer memory read/write and write delayed by ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 57. misaligned single-transfer memory read and write . . . . . . 135 figure 58. burst reads and pipelined burst reads . . . . . . . . . . . . . . . . . 137 figure 59. burst writeback due to cache-line replacement . . . . . . . . . 139 figure 60. basic i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 61. misaligned i/o transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 62. basic hold/hlda operation . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 63. hold-initiated inquire hit to shared or exclusive line . . . 145 figure 64. hold-initiated inquire hit to modified line. . . . . . . . . . . . . 147 figure 65. ahold-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 66. ahold-initiated inquire hit to shared or exclusive line . . 151 figure 67. ahold-initiated inquire hit to modified line . . . . . . . . . . . 153 figure 68. ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 69. boff# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 70. basic locked operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 list of figures xiii 21918b/0october 1999 amd-k6 ? - iii processor data sheet figure 71. locked operation with boff# intervention. . . . . . . . . . . . . . 161 figure 72. interrupt acknowledge operation . . . . . . . . . . . . . . . . . . . . . . 163 figure 73. basic special bus cycle (halt cycle) . . . . . . . . . . . . . . . . . . . . 165 figure 74. shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 75. stop grant and stop clock modes, part 1 . . . . . . . . . . . . . . . . 168 figure 76. stop grant and stop clock modes, part 2 . . . . . . . . . . . . . . . . 169 figure 77. init-initiated transition from protected mode to real mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 78. l1 and l2 cache organization . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 79. l1 cache sector organization. . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 80. write handling control register (whcr) . . . . . . . . . . . . . . . 190 figure 81. write allocate logic mechanisms and conditions . . . . . . . . . 192 figure 82. page flush/invalidate register (pfir)msr c000_0088h . 198 figure 83. uc/wc cacheability control register (uwccr) msr c000_0085h (model 8/[f:8]). . . . . . . . . . . . . . . . . . . . . 206 figure 84. external logic for supporting floating-point exceptions. . . 210 figure 85. smm memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 86. tap state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 87. l2 cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 88. l2 cache sector and line organization . . . . . . . . . . . . . . . . . 238 figure 89. l2 tag or data location - edx . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 90. l2 data - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 91. l2 tag information - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 92. lru byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 93. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 94. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 95. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 96. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . 244 figure 97. clock control state transitions . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 98. suggested component placement . . . . . . . . . . . . . . . . . . . . . . 256 figure 99. pulldown v/i curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 figure 100. pullup v/i curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 figure 101. clk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 figure 102. diagrams key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 103. output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 104. maximum float delay timing . . . . . . . . . . . . . . . . . . . . . . . . . 282 figure 105. input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . 282 figure 106. reset and configuration timing . . . . . . . . . . . . . . . . . . . . . . . 283 figure 107. tck waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 xiv list of figures amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 108. trst# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 figure 109. test signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 figure 110. thermal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 figure 111. power consumption versus thermal resistance . . . . . . . . . . 286 figure 112. processor heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . 287 figure 113. measuring case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 114. voltage regulator placement . . . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 115. airflow for a heatsink with fan . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 116. airflow path in a dual-fan system . . . . . . . . . . . . . . . . . . . . . 290 figure 117. airflow path in an atx form-factor system . . . . . . . . . . . . . 291 figure 118. amd-k6 ? - iii processor top-side view . . . . . . . . . . . . . . . . . . 293 figure 119. amd-k6 ? - iii processor pin-side view . . . . . . . . . . . . . . . . . . 294 figure 120. 321-pin staggered cpga package specification . . . . . . . . . . 298 list of tables xv 21918b/0october 1999 amd-k6 ? - iii processor data sheet list of tables table 1. execution latency and throughput of execution units . . . . . 16 table 2. general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3. general-purpose register doubleword, word, and byte names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. segment registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. amd-k6 ? - iii processor model 9 msrs . . . . . . . . . . . . . . . . . . . 37 table 6. extended feature enable register (efer)Cmodel 9 definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. syscall/sysret target address register (star) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. application segment types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10. system segment and gate types . . . . . . . . . . . . . . . . . . . . . . . . 52 table 11. summary of exceptions and interrupts . . . . . . . . . . . . . . . . . . . 53 table 12. integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 13. floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 14. mmx? instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 15. 3dnow!? instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 16. processor-to-bus clock ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 17. output pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 18. input pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 19. output pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 20. input/output pin float conditions. . . . . . . . . . . . . . . . . . . . . . 125 table 21. test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 22. bus cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 23. special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 24. bus-cycle order during misaligned transfers . . . . . . . . . . . . 134 table 25. a[4:3] address-generation sequence during bursts . . . . . . . 136 table 26. bus-cycle order during misaligned i/o transfers . . . . . . . . . 141 table 27. interrupt acknowledge operation definition. . . . . . . . . . . . . 162 table 28. encodings for special bus cycles . . . . . . . . . . . . . . . . . . . . . . 164 table 29. output signal state after reset . . . . . . . . . . . . . . . . . . . . . . 174 table 30. register state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 31. pwt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 32. pcd signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 33. cache# signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 34. l1 and l2 cache states for read and write accesses . . . . . . 195 table 35. valid l1 and l2 cache states and effect of inquire cycles . 200 table 36. l1 and l2 cache states for snoops, flushes, and invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 37. ewbec settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 38. wc/uc memory type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 xvi list of tables amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 39. valid masks and range sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 40. initial state of registers in smm . . . . . . . . . . . . . . . . . . . . . . . 215 table 41. smm state-save area map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 42. smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 43. i/o trap dword configuration . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 44. i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 45. boundary scan bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 46. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 47. supported tap instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 48. tag versus data selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 49. dr7 len and rw definitions . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 50. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 51. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 52. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 53. typical and maximum power dissipation . . . . . . . . . . . . . . . . 262 table 54. clk switching characteristics for 100-mhz bus operation . 268 table 55. clk switching characteristics for 66-mhz bus operation . . 268 table 56. output delay timings for 100-mhz bus operation . . . . . . . . 270 table 57. input setup and hold timings for 100-mhz bus operation . 272 table 58. output delay timings for 66-mhz bus operation . . . . . . . . . 274 table 59. input setup and hold timings for 66-mhz bus operation . . 276 table 60. reset and configuration signals for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 61. reset and configuration signals for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 62. tck waveform and trst# timing at 25 mhz . . . . . . . . . . . . 280 table 63. test signal timing at 25 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 64. package thermal specification . . . . . . . . . . . . . . . . . . . . . . . . 285 table 65. 321-pin staggered cpga package specification . . . . . . . . . . 297 table 66. valid ordering part number combinations . . . . . . . . . . . . . . 299 21918b/0october 1999 amd-k6 ? - iii processor data sheet revision history xvii revision history date rev description feb 1999 a initial published release oct 1999 b added amd-k6- iii /400afr and amd-k6- iii /450afx opns and corresponding specifications to chapter 14, electrical data, chapter 17, thermal design, and chapter 21, ordering information. changed definition of boundary scan register (bsr) in table 45 on page 229. xviii revision history amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 1 amd-k6 ? - iii processor 1 1amd-k6 ? - iii processor n advanced 6-issue risc86 ? superscalar microarchitecture u ten parallel specialized execution units u multiple sophisticated x86-to-risc86 instruction decoders u advanced two-level branch prediction u speculative execution u out-of-order execution u register renaming and data forwarding u issues up to six risc86 instructions per clock n innovative trilevel cache design u 320-kbyte total internal cache ? internal split, 64-kbyte l1 cache - 32-kbyte instruction cache with additional 20-kbytes of predecode cache - 32-kbyte writeback dual-ported data cache - two-way set associative - mesi protocol support ? internal full-speed, 256-kbyte l2 cache - four-way set associative u multiport internal cache design enabling simultaneous 64-bit reads/writes of l1 and l2 caches u 100-mhz frontside bus to optional level-3 cache on super7? platforms n 3dnow!? technology u additional instructions to improve 3d graphics and multimedia performance u separate multiplier and alu for superscalar instruction execution n compatible with super7 platform u leverages high-speed 100-mhz processor bus u accelerated graphic port (agp) support n high-performance ieee 754-compatible and 854-compatible floating-point unit n high-performance industry-standard mmx? instructions u dual integer alu for superscalar execution n 321-pin ceramic pin grid array (cpga) package n industry-standard system management mode (smm) n ieee 1149.1 boundary scan n x86 binary software compatibility 2 amd-k6 ? - iii processor chapter 1 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the innovative amd-k6 ? -iii processor brings industry-leading performance to pc systems running the extensive installed base of x86 software. its super7? compatible, 321-pin ceramic pin grid array (cpga) package enables the processor to reduce time-to-market by leveraging todays cost-effective, industry-standard infrastructure to deliver a superior-performing pc solution. the AMD-K6-III processor incorporates 3dnow!? technology, a significant innovation to the x86 processor architecture that drives todays personal computers. with 3dnow! technology, new, more powerful hardware and software applications enable a more entertaining and productive pc platform. improvements include fast frame rates on high-resolution scenes, superior modeling of real world environments and physics, life-like images and graphics, and big-screen sound and video. amd has taken a leadership role in developing new instructions that enable exciting new levels of performance and realism. 3dnow! technology was defined and implemented in collaboration with microsoft ? , application developers, and graphics vendors, and has received an enthusiastic reception. it is compatible with todays existing x86 software, is supported by industry-standard apis, and requires no operating system support, thereby enabling a broad class of applications to benefit from 3dnow! technology. to provide state-of-the-art performance, the processor incorporates the innovative and efficient risc86 ? microarchitecture, the largest total internal cache on any shipping x86 processor, a powerful ieee 754-compatible and 854-compatible floating-point execution unit, and a high-performance industry-standard multimedia execution unit for executing mmx? instructions. the processor includes additional high-performance single instruction multiple data (simd) execution resources to support the 3dnow! technology. these techniques have been combined to deliver leading-edge performance on leading consumer and business applications in both the microsoft windows ? 98 and windows nt ? operating environments. the AMD-K6-III processors 6-issue risc86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. advanced design techniques implemented in the AMD-K6-III processor include multiple x86 instruction decode, single-clock internal risc operations, ten execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. in addition, the processor supports advanced branch prediction logic by implementing an 8192-entry branch history table, a branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. these design techniques enable the AMD-K6-III processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 1 amd-k6 ? - iii processor 3 the AMD-K6-III processor is x 86 binary code compatible. amds extensive experience through six generations of x86 processors has been carefully integrated into the processor to enable compatibility with windows 98, windows 95, windows 3.x, windows nt, dos, os/2, unix, solaris, netware ? , vines, and other leading x86 operating systems and applications. the AMD-K6-III processor is super7 and socket 7-compatible. the super7 platform is an extension to the popular and robust socket 7 platform. see super7? platform initiative for more information. amd is the worlds second-leading supplier of windows-compatible pc processors, having shipped more than 120 million x86 microprocessors, including more than 60 million windows-compatible processors. the AMD-K6-III processor is the latest member in this long line of processors. with its combination of state-of-the-art features, industry-leading performance, high-performance 3dnow! technology and multimedia engines, x86 compatibility, and low-cost infrastructure, the AMD-K6-III is the superior choice for performance pcs. 1.1 super7? platform initiative amd and its industry partners launched the super7 platform initiative in order to maintain the competitive vitality of the socket 7 infrastructure through a series of enhancements, including the development of an industry-standard 100-mhz processor bus protocol. in addition to the 100-mhz processor bus protocol, the super7 initiative includes the introduction of chipsets that support the agp specification, and support for a backside l2 cache and frontside l3 cache. currently, over 40 motherboard vendors and all major bios and chipset vendors offer super7-based products. super7? platform enhancements the super7 platform has the following enhancements: n 100-mhz processor bus the AMD-K6-III processor supports a 100-mhz, 800 mbyte/second frontside bus to provide a high-speed interface to super7 platform-based chipsets. the 100-mhz interface to the frontside cache and main system memory speeds up access to the frontside cache and main memory by 50 percent over the 66-mhz socket 7 interfaceresulting in a significant increase of 10% in overall system performance. n accelerated graphics port support agp improves the performance of mid-range pcs that have small amounts of video memory on the graphics card. the industry-standard agp specification enables a 133-mhz graphics interface and will scale to even higher levels of performance. n support for backside l2 and frontside l3 cache the super7 platform has the headroom to support higher-performance amd-k6 processors, with clock speeds 4 amd-k6 ? - iii processor chapter 1 amd-k6 ? - iii processor data sheet 21918b/0october 1999 scaling to 450 mhz and beyond. the super7 platform also supports the AMD-K6-III processor which features a full-speed, internal backside 256-kbyte l2 cache designed to enable new levels of performance to leading-edge desktop systems. this processor also supports an optional 100-mhz frontside external l3 cache for even higher-performance system configurations. super7? platform advantages the super7 platform has the following advantages: n delivers performance and features competitive with alternate platforms at the same clock speed, and at a significantly lower cost n takes advantage of existing system designs for superior value n enables oems and resellers to take advantage of mature, high-volume infrastructure supported by multiple bios, chipset, graphics, and motherboard suppliers n reduces inventory and design costs with one motherboard for a wide range of products n builds on a huge installed base of more than 100 million motherboards n provides an easy upgrade path for future pc users, as well as a bridge to legacy users by taking advantage of the low-cost, mature socket 7 infrastructure, the super7 platform will continue to provide superior value and leading-edge performance for desktop pc systems. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 5 2 internal architecture 2.1 introduction the AMD-K6-III processor implements advanced design techniques known as the risc86 microarchitecture. the risc86 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. this chapter describes the techniques used and the functional elements of the risc86 microarchitecture. 2.2 amd-k6 ? - iii processor microarchitecture overview when discussing processor design, it is important to understand the terms architecture , microarchitecture , and design implementation . the term architecture refers to the instruction set and features of a processor that are visible to software programs running on the processor. the architecture determines what software the processor can run. the architecture of the AMD-K6-III processor is the industry-standard x86 instruction set. the term microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. the amd-k6 family of processors are based on a sophisticated risc core known as the enhanced risc86 microarchitecture. the enhanced risc86 microarchitecture is an advanced, second-order decoupled decode/execution design approach that enables industry-leading performance for x86-based software. the term design implementation refers to the actual logic and circuit designs from which the processor is created according to the microarchitecture specifications. 6 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 enhanced risc86 ? microarchitecture the enhanced risc86 microarchitecture defines the characteristics of the amd-k6 family. the innovative risc86 microarchitecture approach implements the x86 instruction set by internally translating x86 instructions into risc86 operations. these risc86 operations were specially designed to include direct support for the x86 instruction set while observing the risc performance principles of fixed length encoding, regularized instruction fields, and a large register set. the enhanced risc86 microarchitecture used in the AMD-K6-III processor enables higher processor core performance and promotes straightforward extensions, such as those added in the current AMD-K6-III processor and those planned for the future. instead of directly executing complex x86 instructions, which have lengths of 1 to 15 bytes, the AMD-K6-III processor executes the simpler and easier fixed-length risc86 operations, while maintaining the instruction coding efficiencies found in x86 programs. the AMD-K6-III processor contains parallel decoders, a centralized risc86 operation scheduler, and ten execution units that support superscalar operationmultiple decode, execution, and retirementof x86 instructions. these elements are packed into an aggressive and highly efficient six-stage pipeline. amd-k6 ? - iii processor block diagram. as shown in figure 1 on page 7, the high-performance, out-of-order execution engine of the AMD-K6-III processor is mated to a split, level-one, 64-kbyte, writeback cache with 32 kbytes of instruction cache and 32 kbytes of data cache. backing up the level-one cache is a large, unified, level-two, 256-kbyte, writeback cache. the level-one instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. the icu issues and retires risc86 operations contained in the scheduler. the system bus interface is an industry-standard 64-bit super7 and socket 7 demultiplexed bus. the AMD-K6-III processor combines the latest in processor microarchitecture to provide the highest x86 performance for todays personal computers. the AMD-K6-III processor offers true sixth-generation performance and x86 binary software compatibility. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 7 figure 1. amd-k6 ? - iii processor block diagram decoders. decoding of the x86 instructions begins when the on-chip level-one instruction cache is filled. predecode logic determines the length of an x86 instruction on a byte-by-byte basis. this predecode information is stored, along with the x86 instructions, in the level-one instruction cache, to be used later by the decoders. the decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into risc86 operations. note: in this chapter, clock refers to a processor clock. the AMD-K6-III processor categorizes x86 instructions into three types of decodesshort, long, and vector. the decoders process either two short, one long, or one vector decode at a time. the three types of decodes have the following characteristics: n short decodesx86 instructions less than or equal to seven bytes in length n long decodesx86 instructions less than or equal to 11 bytes in length n vector decodescomplex x86 instructions store unit store queue instruction control unit scheduler buffer (24 risc86) six risc86 six risc86 ? ? operation issue operation issue four risc86 decode out-of-order out-of-order execution engine execution engine level-one dual-port data cache (32 kbyte) 128 entry dtlb 32 kbyte level-one instruction cache 20 kbyte predecode cache dual instruction decoders x86 to risc86 16 byte fetch load unit floating- point unit branch resolution unit predecode logic level-one cache controller 100 mhz super7? bus interface level-two cache (256 kbyte) register unit x (integer/ multimedia/3dnow! tm ) register unit y (integer/ multimedia/3dnow!) branch logic (8192-entry bht) (16-entry btc) (16-entry ras) 64 entry itlb 8 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 short and long decodes are processed completely within the decoders. vector decodes are started by the decoders and then completed by fetched sequences from an on-chip rom. after decoding, the risc86 operations are delivered to the scheduler for dispatching to the executions units. scheduler/instruction control unit. the centralized scheduler or buffer is managed by the instruction control unit (icu). the icu buffers and manages up to 24 risc86 operations at a time. this equals from 6 to 12 x86 instructions. this buffer size (24) is perfectly matched to the processors six-stage risc86 pipeline and four risc86-operations decode rate. the scheduler accepts as many as four risc86 operations at a time from the decoders and retires up to four risc86 operations per clock cycle. the icu is capable of simultaneously issuing up to six risc86 operations at a time to the execution units. this consists of the following types of operations: n memory load operation n memory store operation n complex integer, mmx or 3dnow! register operation n simple integer, mmx or 3dnow! register operation n floating-point register operation n branch condition evaluation registers. when managing the 24 risc86 operations, the icu uses 69 physical registers contained within the risc86 microarchitecture. 48 of the physical registers are located in a general register file and are grouped as 24 committed or architectural registers plus 24 rename registers. the 24 architectural registers consist of 16 scratch registers and 8 registers that correspond to the x86 general-purpose registers eax, ebx, ecx, edx, ebp, esp, esi, and edi. there is an analogous set of registers specifically for mmx and 3dnow! operations. there are 9 mmx/3dnow! committed or architectural registers plus 12 mmx/3dnow! rename registers. the 9 architectural registers consist of one scratch register and 8 registers that correspond to the mmx registers (mm0Cmm7), as shown in figure 17 on page 29. branch logic. the AMD-K6-III processor is designed with highly sophisticated dynamic branch logic consisting of the following: n branch history/prediction table n branch target cache n return address stack 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 9 the AMD-K6-III processor implements a two-level branch prediction scheme based on an 8192-entry branch history table. the branch history table stores prediction information that is used for predicting conditional branches. because the branch history table does not store predicted target addresses, special address alus calculate target addresses on-the-fly during instruction decode. the branch target cache augments predicted branch performance by avoiding a one clock cache-fetch penalty. this specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. the return address stack is a unique device specifically designed for optimizing call and return pairs. in summary, the AMD-K6-III processor uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. 3dnow!? technology. amd has taken a lead role in improving the multimedia and 3d capabilities of the x86 processor family with the introduction of 3dnow! technology, which uses a packed, single-precision, floating-point data format and single instruction multiple data (simd) operations based on the mmx technology model. 2.3 cache, instruction prefetch, and predecode bits the writeback level-one cache on the AMD-K6-III processor is organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the level-two cache is 256 kbytes, and is organized as a unified, four-way set- associative cache. the cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. as the level-one instruction cache is filled from the level-two cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecoding logic. predecoding annotates information (5 bits per byte) to each instruction byte that later enables the decoders to efficiently decode multiple instructions simultaneously. cache the processor cache design takes advantage of a sectored organization (see figure 2 on page 10). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate pairs of mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. 10 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 two forms of cache misses and associated cache fills can take placea tag-miss cache fill and a tag-hit cache fill. in the case of a tag-miss cache fill, the level-one cache miss is due to a tag mismatch, in which case the required cache line is filled either from the level-two cache or from external memory, and the level-one cache line within the sector that was not required is marked as invalid. in the case of a tag-hit cache fill, the address matches the tag, but the requested cache line is marked as invalid. the required level-one cache line is filled from the level-two cache or from external memory, and the level-one cache line within the sector that is not required remains in the same cache state. prefetching the AMD-K6-III processor conditionally performs cache prefetching which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. from the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. the 3dnow! technology includes an instruction called prefetch that allows a cache line to be prefetched into the level-one data cache and the level-two cache. the prefetch instruction format is defined in table 15, 3dnow!? instructions, on page 81. for more detailed information, see the 3dnow!? technology manual , order# 21928. predecode bits decoding x86 instructions is particularly difficult because the instructions are variable-length and can be from 1 to 15 bytes long. predecode logic supplies the five predecode bits that are associated with each instruction byte. the predecode bits indicate the number of bytes to the start of the next x86 instruction. the predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in figure 2. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. figure 2. cache sector organization tag address cache line 0 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 11 2.4 instruction fetch and decode instruction fetch the processor can fetch up to 16 bytes per clock out of the level- one instruction cache or branch target cache. the fetched information is placed into a 16-byte instruction buffer that feeds directly into the decoders (see figure 3). fetching can occur along a single execution stream with up to seven outstanding branches taken. the instruction fetch logic is capable of retrieving any 16 contiguous bytes of information within a 32-byte boundary. there is no additional penalty when the 16 bytes of instructions lie across a cache line boundary. the instruction bytes are loaded into the instruction buffer as they are consumed by the decoders. although instructions can be consumed with byte granularity, the instruction buffer is managed on a memory-aligned word (two bytes) organization. therefore, instructions are loaded and replaced with word granularity. when a control transfer occurssuch as a jmp instruction the entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes. figure 3. the instruction buffer 16 instruction bytes plus 16 sets of predecode bits branch-target cache 16 x 16 by tes 2:1 instruction buffer 16 bytes 16 bytes branch target address adders return address stack 16 x 16 bytes 32-kbyte level-one instruction cache fetch unit 12 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 instruction decode the AMD-K6-III processor decode logic is designed to decode multiple x86 instructions per clock (see figure 4). the decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates risc86 operations from these x86 instructions. risc86 operations are fixed-length internal instructions. most risc86 operations execute in a single clock. risc86 operations are combined to perform every function of the x86 instruction set. some x86 instructions are decoded into as few as zero risc86 operationsfor instance a nopor one risc86 operationa register-to-register add. more complex x86 instructions are decoded into several risc86 operations. figure 4. amd-k6 ? - iii processor decode logic instruction buffer 4 risc86 operations long decoder short decoder #1 short decoder #2 vector address vector decoder risc86 ? sequencer on-chip rom 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 13 the AMD-K6-III processor uses a combination of decoders to convert x86 instructions into risc86 operations. the hardware consists of three sets of decoderstwo parallel short decoders, one long decoder, and one vector decoder. the two parallel short decoders translate the most commonly-used x86 instructions (moves, shifts, branches, alu, fpu) and the extensions to the x86 instruction set (including mmx and 3dnow! instructions) into zero, one, or two risc86 operations each. the short decoders only operate on x86 instructions that are up to seven bytes long. in addition, they are designed to decode up to two x86 instructions per clock. the commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long, and semi-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. the long decoder only performs one decode per clock and generates up to four risc86 operations. all other translations (complex instructions, serializing conditions, interrupts and exceptions, etc.) are handled by a combination of the vector decoder and risc86 operation sequences fetched from an on-chip rom. for complex operations, the vector decoder logic provides the first set of risc86 operations and a vector (initial rom address) to a sequence of further risc86 operations. the same types of risc86 operations are fetched from the rom as those that are generated by the hardware decoders. note: although all three sets of decoders are simultaneously fed a copy of the instruction buffer contents, only one of the three types of decoders is used during any one decode clock. the decoders or the on-chip risc86 rom always generate a group of four risc86 operations. for decodes that cannot fill the entire group with four risc86 operations, risc86 nop operations are placed in the empty locations of the grouping. for example, a long-decoded x86 instruction that converts to only three risc86 operations is padded with a single risc86 nop operation and then passed to the scheduler. up to six groups or 24 risc86 operations can be placed in the scheduler at a time. all of the common, and a few of the uncommon, floating-point instructions (also known as esc instructions) are hardware decoded as short decodes. this decode generates a risc86 floating-point operation and, optionally, an associated 14 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 floating-point load or store operation. floating-point or esc instruction decode is only allowed in the first short decoder, but non-esc instructions can be decoded simultaneously by the second short decoder along with an esc instruction decode in the first short decoder. all of the mmx and 3dnow! instructions, with the exception of the emms, femms, and prefetch instructions, are hardware decoded as short decodes. the mmx instruction decode generates a risc86 mmx operation and, optionally, an associated mmx load or store operation. a 3dnow! instruction decode generates a risc86 3dnow! operation and, optionally, an associated load or store operation. mmx and 3dnow! instructions can be decoded in either or both of the short decoders. 2.5 centralized scheduler the scheduler is the heart of the AMD-K6-III processor (see figure 5 on page 15). it contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple risc86 operations, and speculative execution. the schedulers buffer can hold up to 24 risc86 operations. this equates to a maximum of 12 x86 instructions. the scheduler can issue risc86 operations from any of the 24 locations in the buffer. when possible, the scheduler can simultaneously issue a risc86 operation to any available execution unit (store, load, branch, register x integer/multimedia, register y integer/multimedia, or floating-point). in total, the scheduler can issue up to six and retire up to four risc86 operations per clock. the main advantage of the scheduler and its operation buffer is the ability to examine an x86 instruction window equal to 12 x86 instructions at one time. this advantage is due to the fact that the scheduler operates on the risc86 operations in parallel and allows the AMD-K6-III processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. although the scheduler can issue risc86 operations for out-of-order execution, it always retires x86 instructions in order. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 15 figure 5. amd-k6 ? - iii processor scheduler 2.6 execution units the AMD-K6-III processor contains ten parallel execution unitsstore, load, integer x alu, integer y alu, mmx alu (x), mmx alu (y), mmx/3dnow! multiplier, 3dnow! alu, floating-point, and branch condition. each unit is independent and capable of handling the risc86 operations. table 1 on page 16 details the execution units, functions performed within these units, operation latency, and operation throughput. the store and load execution units are two-stage pipelined designs. the store unit performs data writes and register calculation for lea/push. data memory and register writes from stores are available after one clock. store operations are held in a store queue prior to execution. from there, they execute in order. the load unit performs data memory reads. data is available from the load unit after two clocks. risc86 operation buffer risc86 issue buses risc86 #0 risc86 #1 risc86 #2 risc86 #3 centralized risc86 ? operation scheduler from decode logic 16 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the integer x execution unit can operate on all alu operations, multiplies, divides (signed and unsigned), shifts, and rotates. the integer y execution unit can operate on the basic word and doubleword alu operationsadd, and, cmp, or, sub, xor, zero-extend and sign-extend operands. register x and y pipelines the functional units that execute mmx and 3dnow! instructions share pipeline control with the integer x and integer y units. the register x and y functional units are attached to the issue bus for the register x execution pipeline or the issue bus for the register y execution pipeline or both. each register pipeline has dedicated resources that consist of an integer execution unit and an mmx alu execution unit, therefore allowing superscalar operation on integer and mmx instructions. in addition, both the x and y issue buses are connected to the 3dnow! alu, the mmx/3dnow! multiplier and mmx shifter, which allows the appropriate risc86 operation to be issued through either bus. figure 6 on page 17 shows the details of the x and y register pipelines. table 1. execution latency and throughput of execution units functional unit function latency throughput store lea/push, address (pipelined) 1 1 memory store (pipelined) 1 1 load memory loads (pipelined) 2 1 integer x integer alu 1 1 integer multiply 2C3 2C3 integer shift 1 1 multimedia (processes mmx instructions) mmx alu 1 1 mmx shifts, packs, unpack 1 1 mmx multiply 2 1 integer y basic alu (16-bit and 32-bit operands) 1 1 branch resolves branch conditions 1 1 fpu fadd, fsub, fmul 2 2 3dnow! 3dnow! alu 2 1 3dnow! multiply 2 1 3dnow! convert 2 1 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 17 figure 6. register x and y functional units the branch condition unit is separate from the branch prediction logic in that it resolves conditional branches such as jcc and loop after the branch condition has been evaluated. 2.7 branch-prediction logic sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the AMD-K6-III processor. branches in x86 code fit into two categories unconditional branches, which always change program flow (that is, the branches are always taken) and conditional branches, which may or may not divert program flow (that is, the branches are taken or not-taken). when a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. the AMD-K6-III processor branch logic has been designed to handle this type of mmx/ 3dnow! ? multiplier integer x alu mmx ? alu mmx shifter 3dnow! alu mmx alu integer y alu scheduler buffer (24 risc86 ? operations) issue bus for the register x execution pipeline issue bus for the register y execution pipeline 18 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 program behavior and its negative effects on instruction execution, such as stalls due to delayed instruction fetching and the draining of the processor pipeline. the branch logic contains an 8192-entry branch history table, a 16-entry by 16-byte branch target cache, a 16-entry return address stack, and a branch execution unit. branch history table the AMD-K6-III processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. however, conditional branches require the use of the dynamic branch-prediction mechanism built into the AMD-K6-III processor. a two-level adaptive history algorithm is implemented in an 8192-entry branch history table. this table stores executed branch information, predicts individual branches, and predicts the behavior of groups of branches. to accommodate the large branch history table, the AMD-K6-III processor does not store predicted target addresses. instead, the branch target addresses are calculated on-the-fly using alus during the decode stage. the adders calculate all possible target addresses before the instructions are fully decoded and the processor chooses which addresses are valid. branch target cache to avoid a one clock cache-fetch penalty when a branch is predicted taken, a built-in branch target cache supplies the first 16 bytes of instructions directly to the instruction buffer (assuming the target address hits this cache). (see figure 3 on page 11.) the branch target cache is organized as 16 entries of 16 bytes. in total, the branch prediction logic achieves branch prediction rates greater than 95%. return address stack the return address stack is a special device designed to optimize call and ret pairs. software is typically compiled with subroutines that are frequently called from various places in a program. this is usually done to save space. entry into the subroutine occurs with the execution of a call instruction. at that time, the processor pushes the address of the next instruction in memory following the call instruction onto the stack (allocated space in memory). when the processor encounters a ret instruction (within or at the end of the subroutine), the branch logic pops the address from the stack and begins fetching from that location. to avoid the latency of main memory accesses during call and ret operations, the return address stack caches the pushed addresses. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 2 internal architecture 19 branch execution unit the branch execution unit enables efficient speculative execution. this unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. the AMD-K6-III processor does not permanently update the x86 registers or memory locations until all speculatively executed conditional branch instructions are resolved. when a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. the AMD-K6-III processor can support up to seven outstanding branches. 20 internal architecture chapter 2 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 21 3 software environment this chapter provides a general overview of the AMD-K6-III processors x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-III processor architecture and design implementation. the AMD-K6-III processor model 9 implements the same ten msrs as the amd-k6-2 processor model 8/[f:8], and the bits and fields within these ten msrs are defined identically. the AMD-K6-III processor model 9 supports an additional msr for a total of eleven msrs. the name AMD-K6-III processor by itself refers to all steppings of the model 9. see model-specific registers (msr) on page 37 for the msr definitions. 3.1 registers the AMD-K6-III processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, mmx/3dnow!, eflags, control, task, debug, test, and descriptor/memory-management registers. in addition, this chapter provides information on the AMD-K6-III processor msrs. note: areas of the register designated as reserved should not be modified by software. 22 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 general-purpose registers the eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions. table 2 contains a list of the general-purpose registers and the functions for which they are used. in order to support byte and word operations, eax, ebx, ecx, and edx can also be used as 8-bit and 16-bit registers. the shorter registers are overlaid on the longer ones. for example, the name of the 16-bit version of eax is ax (low 16 bits of eax) and the 8-bit names for ax are ah (high order bits) and al (low order bits). the same naming convention applies to ebx, ecx, and edx. edi, esi, esp, and ebp can be used as smaller 16-bit registers called di, si, sp, and bp respectively, but these registers do not have 8-bit versions. figure 7 shows the eax register with its name components, and table 3 lists the doubleword (32-bit) general-purpose registers and their corresponding word (16-bit) and byte (8-bit) versions. figure 7. eax register with 16-bit and 8-bit name components table 2. general-purpose registers register function eax commonly used as an accumulator ebx commonly used as a pointer ecx commonly used for counting in loop operations edx commonly used to hold i/o information and to pass parameters edi commonly used as a destination pointer by the es segment esi commonly used as a source pointer by the ds segment esp used to point to the stack segment ebp used to point to data within the stack segment 87 0 15 16 31 eax ax ah al 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 23 integer data types four types of data are used in general-purpose registersbyte, word, doubleword, and quadword integers. figure 8 shows the format of the integer data registers. figure 8. integer data registers table 3. general-purpose register doubleword, word, and byte names 32-bit name (doubleword) 16-bit name (word) 8-bit name (high-order bits) 8-bit name (low-order bits) eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl edi di CC esi si C C esp sp C C ebp bp C C 15 0 31 0 precision 32 bits precision 16 bits word integer doubleword integer 70 precision 8 bits byte integer 63 0 precision 64 bits quadword integer 24 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 segment registers the six 16-bit segment registers are used as pointers to areas (segments) of memory. table 4 lists the segment registers and their functions. figure 9 shows the format for all six segment registers. figure 9. segment register segment usage the operating system determines the type of memory model that is implemented. the segment register usage is determined by the operating systems memory model. in a real mode memory model the segment register points to the base address in memory. in a protected mode memory model the segment register is called a selector and it selects a segment descriptor in a descriptor table. this descriptor contains a pointer to the base of the segment, the limit of the segment, and various protection attributes. for more information on descriptor formats, see descriptors and gates on page 50. figure 10 on page 25 shows segment usage for real mode and protected mode memory models. table 4. segment registers segment register segment register function cs code segment, where instructions are located ds data segment, where data is located es data segment, where data is located fs data segment, where data is located gs data segment, where data is located ss stack segment 0 15 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 25 figure 10. segment usage instruction pointer the instruction pointer (eip or ip) is used in conjunction with the code segment register (cs). the instruction pointer is either a 32-bit register (eip) or a 16-bit register (ip) that keeps track of where the next instruction resides within memory. this register cannot be directly manipulated, but can be altered by modifying return pointers when a jmp or call instruction is used. floating-point registers the floating-point execution unit in the AMD-K6-III processor is designed to perform mathematical operations on non-integer numbers. this floating-point unit conforms to the ieee 754 and 854 standards and uses several registers to meet these standardseight numeric floating-point registers, a status word register, a control word register, and a tag word register. segment register real mode memory model segment selector physical memory protected mode memory model base descriptor table physical memory segment base base limit base limit segment base 26 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the eight floating-point registers are physically 80 bits wide and labeled fpr0Cfpr7. figure 11 shows the format of these floating-point registers. see floating-point register data types on page 28 for information on allowable floating-point data types. figure 11. floating-point register the 16-bit fpu status word register contains information about the state of the floating-point unit. figure 12 shows the format of this register. figure 12. fpu status word register 64 63 0 78 79 sign exponent significand 9876543210 10 11 12 13 14 15 p e o e e s c 0 c 1 i e z e u e s f tosp c 3 b c 2 d e symbol description bits b fpu busy 15 c3 condition code 14 tosp top of stack pointer 13C11 c2 condition code 10 c1 condition code 9 c0 condition code 8 es error summary status 7 sf stack fault 6 exception flags pe precision error 5 ue underflow error 4 oe overflow error 3 ze zero divide error 2 de denormalized operation error 1 ie invalid operation error 0 tosp information 000 = fpr0 111 = f p r7 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 27 the fpu control word register allows a programmer to manage the fpu processing options. figure 13 shows the format of this register. figure 13. fpu control word register the fpu tag word register contains information about the registers in the register stack. figure 14 shows the format of this register. figure 14. fpu tag word register 9876543210 10 11 12 13 14 15 p m o m p c r c i m z m u m d m rounding control information 00b = round to the nearest or even number 01b = round down toward negative infinity 10b = round up toward positive infinity 11b = truncate toward zero y precision control information 00b = 24 bits single precision real 01b = reserved 10b = 53 bits double precision real 11b = 64 bits extended precision real reserved symbol description bits y infinity bit (80287 compatibility) 12 rc rounding control 11C10 pc precision control 9C8 exception masks pm precision 5 um underflow 4 om overflow 3 zm zero divide 2 dm denormalized operation 1 im invalid operation 0 tag values 00 = valid 01 = zero 10 = special 11 = empty 87 65 43 2 1 0 10 11 12 13 14 15 tag (fpr7) tag (fpr6) tag (fpr4) tag (fpr5) tag (fpr2) tag (fpr3) tag (fpr0) tag (fpr1) 9 28 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 floating-point register data types floating-point registers use four different types of data packed decimal, single-precision real, double-precision real, and extended-precision real. figures 15 and 16 show the formats for these registers. figure 15. packed decimal data register figure 16. precision real data registers 0 79 precision 18 digits, 72 bits used, 4-bits/digit 71 s ignore or zero 78 72 description bits ignored on load, zeros on store 78-72 sign bit 79 0 63 double-precision real 31 0 single-precision real 0 79 22 s biased exponent 78 23 s biased exponent 63 64 51 52 biased exponent s significand significand significand 30 62 extended-precision real s = sign bit s = sign bit s = sign bit i 62 i = integer bit 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 29 mmx?/3dnow!? registers the AMD-K6-III processor implements eight 64-bit mmx/3dnow! registers for use by multimedia software. these registers are mapped on the floating-point register stack. the mmx and 3dnow! instructions refer to these registers as mm0 to mm7. figure 17 shows the format of these registers. for more information, see the amd-k6 ? processor multimedia technology manual , order# 20726 and the 3dnow! technology manual, order# 21928. figure 17. mmx?/3dnow!? registers mmx? data types for the mmx instructions, the mmx registers use three types of datapacked eight-byte integer, packed quadword integer, and packed dual doubleword integer. figure 18 on page 30 shows the format of these data types. 63 0 mm0 mm7 mm1 mm6 mm5 mm2 mm3 mm4 30 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 18. mmx? data types 3dnow!? data types for 3dnow! instructions, the mmx/3dnow! registers use packed single-precision real data. figure 19 shows the format of the 3dnow! data type. figure 19. 3dnow!? data types 63 0 packed bytes integer 63 0 packed words integer 63 0 packed doubleword integer 32 31 48 47 32 31 16 15 56 55 48 47 40 39 32 31 24 23 16 15 8 7 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 word 0 word 1 word 2 word 3 doubleword 1 doubleword 0 63 62 0 32 31 30 packed single precision floating point 55 54 23 22 biased exponent s significand s = sign bit biased exponent s significand s = sign bit 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 31 eflags register the eflags register provides for three different types of flagssystem, control, and status. the system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations. figure 20 shows the format of this register. figure 20. eflags registers 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 i o p l 31 30 29 28 27 26 25 24 23 22 a f p f z f s f i f d f t f o f n t r f v m a c v i f v i p i d c f reserved symbol description bits id id flag 21 vip virtual interrupt pending 20 vif virtual interrupt flag 19 ac alignment check 18 vm virtual-8086 mode 17 rf resume flag 16 nt nested task 14 iopl i/o privilege level 13C12 of overflow flag 11 df direction flag 10 if interrupt flag 9 tf trap flag 8 sf sign flag 7 zf zero flag 6 af auxiliary flag 4 pf parity flag 2 cf carry flag 0 32 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 control registers the five control registers contain system control bits and pointers. figures 21 through 25 show the formats of these registers. figure 21. control register 4 (cr4) figure 22. control register 3 (cr3) figure 23. control register 2 (cr2) 76543210 31 p s e t s d m c e v m e d e p v i reserved symbol description bit mce machine check enable 6 pse page size extensions 4 de debugging extensions 3 tsd time stamp disable 2 pvi protected virtual interrupts 1 vme virtual-8086 mode extensions 0 p c d 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 page directory base p w t reserved symbol description bit pcd page cache disable 4 pwt page writethrough 3 0 31 page fault linear address 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 33 figure 24. control register 1 (cr1) figure 25. control register 0 (cr0) 0 31 reserved e t t s 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 a m e m w p m p p e n e p g c d n w reserved symbol description bit am alignment mask 18 wp write protect 16 ne numeric error 5 et extension type 4 ts task switched 3 em emulation 2 mp monitor co-processor 1 pe protection enabled 0 symbol description bit pg paging 31 cd cache disable 30 nw not writethrough 29 34 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 debug registers figures 26 through 29 show the 32-bit debug registers supported by the processor. figure 26. debug register dr7 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 g 0 g 1 l 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 reserved symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0 symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 35 figure 27. debug register dr6 figure 28. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 b t b d b 3 reserved symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4 36 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 29. debug registers dr3, dr2, dr1, and dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 37 model-specific registers (msr) the AMD-K6-III processor provides eleven msrs. the value in the ecx register selects the msr to be addressed by the rdmsr and wrmsr instructions. the values in eax and edx are used as inputs and outputs by the rdmsr and wrmsr instructions. table 5 lists the msrs and the corresponding value of the ecx register. figures 30 through 42 show the msr formats. for more information about the msrs, see the amd-k6 ? processor bios design application note , order# 21329. for more information about the rdmsr and wrmsr instructions, see the amd k86? family bios and software tools development guide , order# 21062. mcar and mctr. the AMD-K6-III processor does not support the generation of a machine check exception. however, the processor does provide a 64-bit machine check address register (mcar), a 64-bit machine check type register (mctr), and a machine check enable (mce) bit in cr4. because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). table 5. amd-k6 ? - iii processor model 9 msrs model-specific register value of ecx machine check address register (mcar) 00h machine check type register (mctr) 01h test register 12 (tr12) 0eh time stamp counter (tsc) 10h extended feature enable register (efer) c000_0080h syscall/sysret target address register (star) c000_0081h write handling control register (whcr) c000_0082h uc/wc cacheability control register (uwccr) c000_0085h processor state observability register (psor) c000_0087h page flush/invalidate register (pfir) c000_0088h level-2 cache array register (l2aar) c000_0089h 38 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 30. machine-check address register (mcar) figure 31. machine-check type register (mctr) test register 12 (tr12). test register 12 provides a method for disabling the l1 caches. figure 32 shows the format of tr12. figure 32. test register 12 (tr12) time stamp counter. with each processor clock cycle, the processor increments the 64-bit time stamp counter (tsc) msr. figure 33 shows the format of the tsc. figure 33. time stamp counter (tsc) 0 63 mcar 54 0 63 mctr reserved 4210 63 c i 3 reserved symbol description bit ci cache inhibit bit 3 0 63 tsc 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 39 extended feature enable register (efer). the extended feature enable register (efer) contains the control bits that enable the extended features of the processor. figure 34 shows the format of the efer register, and table 6 defines the function of each bit of the efer register. figure 34. extended feature enable register (efer)msr c000_0080h table 6. extended feature enable register (efer)Cmodel 9 definition for more information on ewbec, see ewbe control on page 203 bit description r/w function 63C5 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 4l2dr/w if l2d is set to 1, the l2 cache is completely disabled. this bit is provided for debug and testing purposes. for normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). 3-2 ewbe control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe disable (gewbed) and speculative ewbe disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting following reset). if enabled, cache misses initiated by a memory read within a 32-byte line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec symbol description bi t l2d l2 cache disable 4 ewbec ewbe control 3-2 dpe data prefetch enable 1 sce system call extension 0 5 l 2 d 40 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 syscall/sysret target address register (star). the syscall/sysret target address register (star) contains the target eip address used by the syscall instruction and the 16-bit code and stack segment selector bases used by the syscall and sysret instructions. figure 35 shows the format of the star register, and table 7 defines the function of each bit of the star register. for more information, see the syscall and sysret instruction specification application note , order# 21086. figure 35. syscall/sysret target address register (star) write handling control register (whcr). the write handling control register (whcr) is a msr that contains two fieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 36). for more information, see write allocate on page 189. note: the whcr register as defined in the model 9 is the same as the model 8/[f:8]. 31 0 63 target eip address 32 47 48 syscall cs selector and ss selector base sysret cs selector and ss selector base table 7. syscall/sysret target address register (star) definition bit description r/w 63C48 sysret cs and ss selector base r/w 47C32 syscall cs and ss selector base r/w 31C0 target eip address r/w 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 41 figure 36. write handling control register (whcr)msr c0000_0082h uc/wc cacheability control register (uwccr). the AMD-K6-III processor provides two variable-range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as uncacheable (uc) or write-combining (wc) memory. for more information, see memory type range registers on page 205. . figure 37. uc/wc cacheability control register (uwccr) msr c0000_0085h processor state observability register (psor). the AMD-K6-III processor provides the processor state observability register (psor) (see figure 38). 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33 42 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 . figure 38. processor state observability register (psor ) msr c000_0087h page flush/invalidate register (pfir). the AMD-K6-III processor contains the page flush/invalidate register (pfir) (see figure 39) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space. for more detailed information on pfir, see pfir on page 198. figure 39. page flush/invalidate register (pfir) msr c000_0088h level-2 cache array access register (l2aar). the AMD-K6-III processor provides the l2aar register that allows for direct access to the l2 cache and l2 tag arrays. the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 40). 20 63 bf reserved symbol description bit nol2 no l2 functionality 8 step processor stepping 7-4 bf bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2 linpage 10 63 f / i reserved symbol description bit linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 43 figure 40. l2 tag or data location - edx if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format as illustrated in figure 41. similarly, if the l2 cache data is written, the write data is taken from eax. figure 41. l2 data - eax reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 0 31 data 44 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 42. similarly, if the l2 tag is written, the write data is taken from eax. figure 42. l2 tag information - eax for more detailed information, refer to l2 cache and tag array testing on page 237. c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 45 memory management registers the AMD-K6-III processor controls segmented memory management with the registers listed in table 8. figure 43 on page 45 shows the formats of these registers. figure 43. memory management registers table 8. memory management registers register name function global descriptor table register contains a pointer to the base of the global descriptor table interrupt descriptor table register contains a pointer to the base of the interrupt descriptor table local descriptor table register contains a pointer to the local descriptor table of the current task task register contains a pointer to the task state segment of the current task 15 0 16-bit limit 16 47 32-bit linear base address global and interrupt descriptor table registers 31 0 63 32-bit limit 32 32-bit linear base address 15 0 local descriptor table register and task register attributes 15 0 selector 46 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 task state segment figure 44 shows the format of the task state segment (tss). figure 44. task state segment (tss) 31 interrupt redirection bitmap (irb) (eight 32-bit locations) 0 i/o permission bitmap (iopb) (up to 8 kbytes) operating system data structure base address of iopb ldt selector 0000h 0000h 0000h 0000h 0000h 0000h 0000h gs fs ds ss cs es edi esi ebp esp ebx edx ecx eax cr3 eflags eip 0000h 0000h 0000h 0000h ss2 ss1 ss0 link (prior tss selector) esp0 esp1 esp2 tss limit from tr 64h 0 t 0000h 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 47 paging the AMD-K6-III processor can physically address up to four gbytes of memory. this memory can be segmented into pages. the size of these pages is determined by the operating system design and the values set up in the page directory entries (pde) and page table entries (pte). the processor can access both 4-kbyte pages and 4-mbyte pages, and the page sizes can be intermixed within a page directory. when the page size extension (pse) bit in cr4 is set, the processor translates linear addresses using either the 4-kbyte translation lookaside buffer (tlb) or the 4-mbyte tlb, depending on the state of the page size (ps) bit in the page directory entry. figures 45 and 46 show how 4-kbyte and 4-mbyte page translations work. figure 45. 4-kbyte paging mechanism linear address page directory page table 4-kbyte page frame cr3 0 11 12 21 31 22 page directory offset page table offset page offset pde pte physical address 48 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 46. 4-mbyte paging mechanism figures 47 through 49 show the formats of the pde and pte. these entries contain information regarding the location of pages and their status. linear address page directory 4-mbyte page frame cr3 0 21 31 22 page directory offset page offset pde physical address 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 49 figure 47. page directory entry 4-kbyte page table (pde) figure 48. page directory entry 4-mbyte page table (pde) 876543210 31 p c d u / s w / r 9 10 11 12 a v l 0 a p w t p page table base address symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 876543210 31 p c d u / s w / r 9 10 11 12 a v l 1 a p w t p physical page base address reserved 21 22 symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 50 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 49. page table entry (pte) descriptors and gates there are various types of structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and gates. these structures are called descriptors. figure 50 on page 51 shows the application segment descriptor format. table 9 contains information describing the memory segment type to which the descriptor points. the application segment descriptor is used to point to either a data or code segment. figure 51 on page 52 shows the system segment descriptor format. table 10 contains information describing the type of segment or gate to which the descriptor points. the system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. the AMD-K6-III processor uses gates to transfer control between executable segments with different privilege levels. figure 52 on page 53 shows the format of the gate descriptor types. table 10 contains information describing the type of segment or gate to which the descriptor points. 876543210 31 p c d u / s w / r 9 10 11 12 a v l a p w t p physical page base address d symbol description bits avl available to software 11C9 reserved 8C7 d dirty 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 51 figure 50. application segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 1 type a v l g d base address 31C24 base address 23C16 reserved symbol description bits g granularity 23 d 32-bit/16-bit 22 avl available to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 9 11-8 table 9. application segment types type data/code description 0 data read-only 1 read-onlyaccessed 2 read/write 3 read/writeaccessed 4 read-onlyexpand-down 5 read-onlyexpand-down, accessed 6 read/writeexpand-down 7 read/writeexpand-down, accessed 8 code execute-only 9 execute-onlyaccessed a execute/read b execute/readaccessed c execute-onlyconforming d execute-onlyconforming, accessed e execute/read-onlyconforming f execute/read-onlyconforming, accessed 52 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 51. system segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 0 type a v l g x base address 31C24 base address 23C16 reserved symbol description bits g granularity 23 x not needed 22 avl availability to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 10 11-8 table 10. system segment and gate types type description 0 reserved 1 available 16-bit tss 2ldt 3 busy 16-bit tss 4 16-bit call gate 5 task gate 6 16-bit interrupt gate 7 16-bit trap gate 8 reserved 9 available 32-bit tss a reserved b busy 32-bit tss c 32-bit call gate d reserved e 32-bit interrupt gate f 32-bit trap gate 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 53 figure 52. gate descriptor exceptions and interrupts table 11 summarizes the exceptions and interrupts. dpl 0 type offset 31C16 p segment selector offset 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved symbol description bits p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 10 11-8 table 11. summary of exceptions and interrupts interrupt number interrupt type cause 0 divide by zero error div, idiv 1 debug debug trap or fault 2 non-maskable interrupt nmi signal sampled asserted 3 breakpoint int 3 4 overflow into 5 bounds check bound 6 invalid opcode invalid instruction 7 device not available esc and wait 8 double fault fault occurs while handling a fault 9 reserved - interrupt 13 10 invalid tss task switch to an invalid segment 11 segment not present instruction loads a segment and present bit is 0 (invalid segment) 12 stack segment stack operation causes limit violation or present bit is 0 13 general protection segment related or miscellaneous invalid actions 14 page fault page protection violation or a reference to missing page 16 floating-point error arithmetic error generated by floating-point instruction 17 alignment check data reference to an unaligned operand. (the ac flag and the am bit of cr0 are set to 1.) 0C255 software interrupt int n 54 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 3.2 instructions supported by the amd-k6 ? - iii processor this section documents all of the x86 instructions supported by the AMD-K6-III processor. the following tables show the instruction mnemonic, opcode, modr/m byte, decode type, and risc86 operation(s) for each instruction. tables 12 through 15 define the integer, floating-point, mmx, and 3dnow! instructions for the AMD-K6-III processor, respectively. the first column in these tables indicates the instruction mnemonic and operand types with the following notations: n reg8 byte integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte n mreg8 byte integer register or byte integer value in memory defined by the modr/m byte n reg16/32 word or doubleword integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte n mreg16/32 word or doubleword integer register, or word or doubleword integer value in memory defined by the modr/m byte n mem8 byte integer value in memory n mem16/32 word or doubleword integer value in memory n mem32/48 doubleword or 48-bit integer value in memory n mem48 48-bit integer value in memory n mem64 64-bit value in memory n imm8 8-bit immediate value n imm16/32 16-bit or 32-bit immediate value n disp8 8-bit displacement value n disp16/32 16-bit or 32-bit displacement value n disp32/48 doubleword or 48-bit displacement value n exx register width depending on the operand size n mem32real 32-bit floating-point value in memory n mem64real 64-bit floating-point value in memory n mem80real 80-bit floating-point value in memory n mmreg mmx/3dnow! register n mmreg1 mmx/3dnow! register defined by bits 5, 4, and 3 of the modr/m byte n mmreg2 mmx/3dnow! register defined by bits 2, 1, and 0 of the modr/m byte 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 55 the second and third columns list all applicable opcode bytes. the fourth column lists the modr/m byte when used by the instruction. the modr/m byte defines the instruction as a register or memory form. if modr/m bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. the fifth column lists the type of instruction decodeshort, long, and vector. the AMD-K6-III processor decode logic can process two short, one long, or one vector decode per clock. the sixth column lists the type of risc86 operation(s) required for the instruction. the operation types and corresponding execution units are as follows: n load, fload, mload load unit n store, fstore, mstore store unit n alu either of the integer execution units n alux integer x execution unit only n branch branch condition unit n float floating-point execution unit n meu multimedia execution units for mmx and 3dnow! instructions n limm load immediate, instruction control unit table 12. integer instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 operations aaa 37h vector aad d5h 0ah vector aam d4h 0ah vector aas 3fh vector adc mreg8, reg8 10h 11-xxx-xxx vector adc mem8, reg8 10h mm-xxx-xxx vector adc mreg16/32, reg16/32 11h 11-xxx-xxx vector adc mem16/32, reg16/32 11h mm-xxx-xxx vector adc reg8, mreg8 12h 11-xxx-xxx vector adc reg8, mem8 12h mm-xxx-xxx vector adc reg16/32, mreg16/32 13h 11-xxx-xxx vector adc reg16/32, mem16/32 13h mm-xxx-xxx vector adc al, imm8 14h vector 56 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 adc eax, imm16/32 15h vector adc mreg8, imm8 80h 11-010-xxx vector adc mem8, imm8 80h mm-010-xxx vector adc mreg16/32, imm16/32 81h 11-010-xxx vector adc mem16/32, imm16/32 81h mm-010-xxx vector adc mreg16/32, imm8 (signed ext.) 83h 11-010-xxx vector adc mem16/32, imm8 (signed ext.) 83h mm-010-xxx vector add mreg8, reg8 00h 11-xxx-xxx short alux add mem8, reg8 00h mm-xxx-xxx long load, alux, store add mreg16/32, reg16/32 01h 11-xxx-xxx short alu add mem16/32, reg16/32 01h mm-xxx-xxx long load, alu, store add reg8, mreg8 02h 11-xxx-xxx short alux add reg8, mem8 02h mm-xxx-xxx short load, alux add reg16/32, mreg16/32 03h 11-xxx-xxx short alu add reg16/32, mem16/32 03h mm-xxx-xxx short load, alu add al, imm8 04h short alux add eax, imm16/32 05h short alu add mreg8, imm8 80h 11-000-xxx short alux add mem8, imm8 80h mm-000-xxx long load, alux, store add mreg16/32, imm16/32 81h 11-000-xxx short alu add mem16/32, imm16/32 81h mm-000-xxx long load, alu, store add mreg16/32, imm8 (signed ext.) 83h 11-000-xxx short alux add mem16/32, imm8 (signed ext.) 83h mm-000-xxx long load, alux, store and mreg8, reg8 20h 11-xxx-xxx short alux and mem8, reg8 20h mm-xxx-xxx long load, alux, store and mreg16/32, reg16/32 21h 11-xxx-xxx short alu and mem16/32, reg16/32 21h mm-xxx-xxx long load, alu, store and reg8, mreg8 22h 11-xxx-xxx short alux and reg8, mem8 22h mm-xxx-xxx short load, alux and reg16/32, mreg16/32 23h 11-xxx-xxx short alu and reg16/32, mem16/32 23h mm-xxx-xxx short load, alu and al, imm8 24h short alux and eax, imm16/32 25h short alu table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 57 and mreg8, imm8 80h 11-100-xxx short alux and mem8, imm8 80h mm-100-xxx long load, alux, store and mreg16/32, imm16/32 81h 11-100-xxx short alu and mem16/32, imm16/32 81h mm-100-xxx long load, alu, store and mreg16/32, imm8 (signed ext.) 83h 11-100-xxx short alux and mem16/32, imm8 (signed ext.) 83h mm-100-xxx long load, alux, store arpl mreg16, reg16 63h 11-xxx-xxx vector arpl mem16, reg16 63h mm-xxx-xxx vector bound 62h vector bsf reg16/32, mreg16/32 0fh bch 11-xxx-xxx vector bsf reg16/32, mem16/32 0fh bch mm-xxx-xxx vector bsr reg16/32, mreg16/32 0fh bdh 11-xxx-xxx vector bsr reg16/32, mem16/32 0fh bdh mm-xxx-xxx vector bswap eax 0fh c8h long alu bswap ecx 0fh c9h long alu bswap edx 0fh cah long alu bswap ebx 0fh cbh long alu bswap esp 0fh cch long alu bswap ebp 0fh cdh long alu bswap esi 0fh ceh long alu bswap edi 0fh cfh long alu bt mreg16/32, reg16/32 0fh a3h 11-xxx-xxx vector bt mem16/32, reg16/32 0fh a3h mm-xxx-xxx vector bt mreg16/32, imm8 0fh bah 11-100-xxx vector bt mem16/32, imm8 0fh bah mm-100-xxx vector btc mreg16/32, reg16/32 0fh bbh 11-xxx-xxx vector btc mem16/32, reg16/32 0fh bbh mm-xxx-xxx vector btc mreg16/32, imm8 0fh bah 11-111-xxx vector btc mem16/32, imm8 0fh bah mm-111-xxx vector btr mreg16/32, reg16/32 0fh b3h 11-xxx-xxx vector btr mem16/32, reg16/32 0fh b3h mm-xxx-xxx vector btr mreg16/32, imm8 0fh bah 11-110-xxx vector btr mem16/32, imm8 0fh bah mm-110-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 58 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 bts mreg16/32, reg16/32 0fh abh 11-xxx-xxx vector bts mem16/32, reg16/32 0fh abh mm-xxx-xxx vector bts mreg16/32, imm8 0fh bah 11-101-xxx vector bts mem16/32, imm8 0fh bah mm-101-xxx vector call full pointer 9ah vector call near imm16/32 e8h short store call mem16:16/32 ffh 11-011-xxx vector call near mreg32 (indirect) ffh 11-010-xxx vector call near mem32 (indirect) ffh mm-010-xxx vector cbw/cwde eax 98h vector clc f8h vector cld fch vector cli fah vector clts 0fh 06h vector cmc f5h vector cmp mreg8, reg8 38h 11-xxx-xxx short alux cmp mem8, reg8 38h mm-xxx-xxx short load, alux cmp mreg16/32, reg16/32 39h 11-xxx-xxx short alu cmp mem16/32, reg16/32 39h mm-xxx-xxx short load, alu cmp reg8, mreg8 3ah 11-xxx-xxx short alux cmp reg8, mem8 3ah mm-xxx-xxx short load, alux cmp reg16/32, mreg16/32 3bh 11-xxx-xxx short alu cmp reg16/32, mem16/32 3bh mm-xxx-xxx short load, alu cmp al, imm8 3ch short alux cmp eax, imm16/32 3dh short alu cmp mreg8, imm8 80h 11-111-xxx short alux cmp mem8, imm8 80h mm-111-xxx short load, alux cmp mreg16/32, imm16/32 81h 11-111-xxx short alu cmp mem16/32, imm16/32 81h mm-111-xxx short load, alu cmp mreg16/32, imm8 (signed ext.) 83h 11-111-xxx long load, alu cmp mem16/32, imm8 (signed ext.) 83h mm-111-xxx long load, alu cmpsb mem8, mem8 a6h vector cmpsw mem16, mem32 a7h vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 59 cmpsd mem32, mem32 a7h vector cmpxchg mreg8, reg8 0fh b0h 11-xxx-xxx vector cmpxchg mem8, reg8 0fh b0h mm-xxx-xxx vector cmpxchg mreg16/32, reg16/32 0fh b1h 11-xxx-xxx vector cmpxchg mem16/32, reg16/32 0fh b1h mm-xxx-xxx vector cmpxchg8b edx:eax 0fh c7h 11-xxx-xxx vector cmpxchg8b mem64 0fh c7h mm-xxx-xxx vector cpuid 0fh a2h vector cwd/cdq edx, eax 99h vector daa 27h vector das 2fh vector dec eax 48h short alu dec ecx 49h short alu dec edx 4ah short alu dec ebx 4bh short alu dec esp 4ch short alu dec ebp 4dh short alu dec esi 4eh short alu dec edi 4fh short alu dec mreg8 feh 11-001-xxx vector dec mem8 feh mm-001-xxx long load, alux, store dec mreg16/32 ffh 11-001-xxx vector dec mem16/32 ffh mm-001-xxx long load, alu, store div al, mreg8 f6h 11-110-xxx vector div al, mem8 f6h mm-110-xxx vector div eax, mreg16/32 f7h 11-110-xxx vector div eax, mem16/32 f7h mm-110-xxx vector idiv mreg8 f6h 11-111-xxx vector idiv mem8 f6h mm-111-xxx vector idiv eax, mreg16/32 f7h 11-111-xxx vector idiv eax, mem16/32 f7h mm-111-xxx vector imul reg16/32, imm16/32 69h 11-xxx-xxx vector imul reg16/32, mreg16/32, imm16/32 69h 11-xxx-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 60 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 imul reg16/32, mem16/32, imm16/32 69h mm-xxx-xxx vector imul reg16/32, imm8 (sign extended) 6bh 11-xxx-xxx vector imul reg16/32, mreg16/32, imm8 (signed) 6bh 11-xxx-xxx vector imul reg16/32, mem16/32, imm8 (signed) 6bh mm-xxx-xxx vector imul ax, al, mreg8 f6h 11-101-xxx vector imul ax, al, mem8 f6h mm-101-xxx vector imul edx:eax, eax, mreg16/32 f7h 11-101-xxx vector imul edx:eax, eax, mem16/32 f7h mm-101-xxx vector imul reg16/32, mreg16/32 0fh afh 11-xxx-xxx vector imul reg16/32, mem16/32 0fh afh mm-xxx-xxx vector in al, imm8 e4h vector in ax, imm8 e5h vector in eax, imm8 e5h vector in al, dx ech vector in ax, dx edh vector in eax, dx edh vector inc eax 40h short alu inc ecx 41h short alu inc edx 42h short alu inc ebx 43h short alu inc esp 44h short alu inc ebp 45h short alu inc esi 46h short alu inc edi 47h short alu inc mreg8 feh 11-000-xxx vector inc mem8 feh mm-000-xxx long load, alux, store inc mreg16/32 ffh 11-000-xxx vector inc mem16/32 ffh mm-000-xxx long load, alu, store invd 0fh 08h vector invlpg 0fh 01h mm-111-xxx vector jo short disp8 70h short branch jb/jnae short disp8 71h short branch table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 61 jno short disp8 71h short branch jnb/jae short disp8 73h short branch jz/je short disp8 74h short branch jnz/jne short disp8 75h short branch jbe/jna short disp8 76h short branch jnbe/ja short disp8 77h short branch js short disp8 78h short branch jns short disp8 79h short branch jp/jpe short disp8 7ah short branch jnp/jpo short disp8 7bh short branch jl/jnge short disp8 7ch short branch jnl/jge short disp8 7dh short branch jle/jng short disp8 7eh short branch jnle/jg short disp8 7fh short branch jcxz/jec short disp8 e3h vector jo near disp16/32 0fh 80h short branch jno near disp16/32 0fh 81h short branch jb/jnae near disp16/32 0fh 82h short branch jnb/jae near disp16/32 0fh 83h short branch jz/je near disp16/32 0fh 84h short branch jnz/jne near disp16/32 0fh 85h short branch jbe/jna near disp16/32 0fh 86h short branch jnbe/ja near disp16/32 0fh 87h short branch js near disp16/32 0fh 88h short branch jns near disp16/32 0fh 89h short branch jp/jpe near disp16/32 0fh 8ah short branch jnp/jpo near disp16/32 0fh 8bh short branch jl/jnge near disp16/32 0fh 8ch short branch jnl/jge near disp16/32 0fh 8dh short branch jle/jng near disp16/32 0fh 8eh short branch jnle/jg near disp16/32 0fh 8fh short branch jmp near disp16/32 (direct) e9h short branch jmp far disp32/48 (direct) eah vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 62 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 jmp disp8 (short) ebh short branch jmp far mreg32 (indirect) efh 11-101-xxx vector jmp far mem32 (indirect) efh mm-101-xxx vector jmp near mreg16/32 (indirect) ffh 11-100-xxx vector jmp near mem16/32 (indirect) ffh mm-100-xxx vector lahf 9fh vector lar reg16/32, mreg16/32 0fh 02h 11-xxx-xxx vector lar reg16/32, mem16/32 0fh 02h mm-xxx-xxx vector lds reg16/32, mem32/48 c5h mm-xxx-xxx vector lea reg16/32, mem16/32 8dh mm-xxx-xxx short load, alu leave c9h long load, alu, alu les reg16/32, mem32/48 c4h mm-xxx-xxx vector lfs reg16/32, mem32/48 0fh b4h vector lgdt mem48 0fh 01h mm-010-xxx vector lgs reg16/32, mem32/48 0fh b5h vector lidt mem48 0fh 01h mm-011-xxx vector lldt mreg16 0fh 00h 11-010-xxx vector lldt mem16 0fh 00h mm-010-xxx vector lmsw mreg16 0fh 01h 11-100-xxx vector lmsw mem16 0fh 01h mm-100-xxx vector lodsb al, mem8 ach long load, alu lodsw ax, mem16 adh long load, alu lodsd eax, mem32 adh long load, alu loop disp8 e2h short alu, branch loope/loopz disp8 e1h vector loopne/loopnz disp8 e0h vector lsl reg16/32, mreg16/32 0fh 03h 11-xxx-xxx vector lsl reg16/32, mem16/32 0fh 03h mm-xxx-xxx vector lss reg16/32, mem32/48 0fh b2h mm-xxx-xxx vector ltr mreg16 0fh 00h 11-011-xxx vector ltr mem16 0fh 00h mm-011-xxx vector mov mreg8, reg8 88h 11-xxx-xxx short alux mov mem8, reg8 88h mm-xxx-xxx short store table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 63 mov mreg16/32, reg16/32 89h 11-xxx-xxx short alu mov mem16/32, reg16/32 89h mm-xxx-xxx short store mov reg8, mreg8 8ah 11-xxx-xxx short alux mov reg8, mem8 8ah mm-xxx-xxx short load mov reg16/32, mreg16/32 8bh 11-xxx-xxx short alu mov reg16/32, mem16/32 8bh mm-xxx-xxx short load mov mreg16, segment reg 8ch 11-xxx-xxx long load mov mem16, segment reg 8ch mm-xxx-xxx vector mov segment reg, mreg16 8eh 11-xxx-xxx vector mov segment reg, mem16 8eh mm-xxx-xxx vector mov al, mem8 a0h short load mov eax, mem16/32 a1h short load mov mem8, al a2h short store mov mem16/32, eax a3h short store mov al, imm8 b0h short limm mov cl, imm8 b1h short limm mov dl, imm8 b2h short limm mov bl, imm8 b3h short limm mov ah, imm8 b4h short limm mov ch, imm8 b5h short limm mov dh, imm8 b6h short limm mov bh, imm8 b7h short limm mov eax, imm16/32 b8h short limm mov ecx, imm16/32 b9h short limm mov edx, imm16/32 bah short limm mov ebx, imm16/32 bbh short limm mov esp, imm16/32 bch short limm mov ebp, imm16/32 bdh short limm mov esi, imm16/32 beh short limm mov edi, imm16/32 bfh short limm mov mreg8, imm8 c6h 11-000-xxx short limm mov mem8, imm8 c6h mm-000-xxx long store mov mreg16/32, imm16/32 c7h 11-000-xxx short limm table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 64 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 mov mem16/32, imm16/32 c7h mm-000-xxx long store movsb mem8,mem8 a4h long load, store, alux, alux movsd mem16, mem16 a5h long load, store, alu, alu movsw mem32, mem32 a5h long load, store, alu, alu movsx reg16/32, mreg8 0fh beh 11-xxx-xxx short alu movsx reg16/32, mem8 0fh beh mm-xxx-xxx short load, alu movsx reg32, mreg16 0fh bfh 11-xxx-xxx short alu movsx reg32, mem16 0fh bfh mm-xxx-xxx short load, alu movzx reg16/32, mreg8 0fh b6h 11-xxx-xxx short alu movzx reg16/32, mem8 0fh b6h mm-xxx-xxx short load, alu movzx reg32, mreg16 0fh b7h 11-xxx-xxx short alu movzx reg32, mem16 0fh b7h mm-xxx-xxx short load, alu mul al, mreg8 f6h 11-100-xxx vector mul al, mem8 f6h mm-100-xxx vector mul eax, mreg16/32 f7h 11-100-xxx vector mul eax, mem16/32 f7h mm-100-xxx vector neg mreg8 f6h 11-011-xxx short alux neg mem8 f6h mm-011-xxx vector neg mreg16/32 f7h 11-011-xxx short alu neg mem16/32 f7h mm-011-xxx vector nop (xchg eax, eax) 90h short limm not mreg8 f6h 11-010-xxx short alux not mem8 f6h mm-010-xxx vector not mreg16/32 f7h 11-010-xxx short alu not mem16/32 f7h mm-010-xxx vector or mreg8, reg8 08h 11-xxx-xxx short alux or mem8, reg8 08h mm-xxx-xxx long load, alux, store or mreg16/32, reg16/32 09h 11-xxx-xxx short alu or mem16/32, reg16/32 09h mm-xxx-xxx long load, alu, store or reg8, mreg8 0ah 11-xxx-xxx short alux or reg8, mem8 0ah mm-xxx-xxx short load, alux or reg16/32, mreg16/32 0bh 11-xxx-xxx short alu or reg16/32, mem16/32 0bh mm-xxx-xxx short load, alu table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 65 or al, imm8 0ch short alux or eax, imm16/32 0dh short alu or mreg8, imm8 80h 11-001-xxx short alux or mem8, imm8 80h mm-001-xxx long load, alux, store or mreg16/32, imm16/32 81h 11-001-xxx short alu or mem16/32, imm16/32 81h mm-001-xxx long load, alu, store or mreg16/32, imm8 (signed ext.) 83h 11-001-xxx short alux or mem16/32, imm8 (signed ext.) 83h mm-001-xxx long load, alux, store out imm8, al e6h vector out imm8, ax e7h vector out imm8, eax e7h vector out dx, al eeh vector out dx, ax efh vector out dx, eax efh vector pop es 07h vector pop ss 17h vector pop ds 1fh vector pop fs 0fh a1h vector pop gs 0fh a9h vector pop eax 58h short load, alu pop ecx 59h short load, alu pop edx 5ah short load, alu pop ebx 5bh short load, alu pop esp 5ch short load, alu pop ebp 5dh short load, alu pop esi 5eh short load, alu pop edi 5fh short load, alu pop mreg 16/32 8fh 11-000-xxx short load, alu pop mem 16/32 8fh mm-000-xxx long load, store, alu popa/popad 61h vector popf/popfd 9dh vector push es 06h long load, store push cs 0eh vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 66 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 push fs 0fh a0h vector push gs 0fh a8h vector push ss 16h vector push ds 1eh long load, store push eax 50h short store push ecx 51h short store push edx 52h short store push ebx 53h short store push esp 54h short store push ebp 55h short store push esi 56h short store push edi 57h short store push imm8 6ah long store push imm16/32 68h long store push mreg16/32 ffh 11-110-xxx vector push mem16/32 ffh mm-110-xxx long load, store pusha/pushad 60h vector pushf/pushfd 9ch vector rcl mreg8, imm8 c0h 11-010-xxx vector rcl mem8, imm8 c0h mm-010-xxx vector rcl mreg16/32, imm8 c1h 11-010-xxx vector rcl mem16/32, imm8 c1h mm-010-xxx vector rcl mreg8, 1 d0h 11-010-xxx vector rcl mem8, 1 d0h mm-010-xxx vector rcl mreg16/32, 1 d1h 11-010-xxx vector rcl mem16/32, 1 d1h mm-010-xxx vector rcl mreg8, cl d2h 11-010-xxx vector rcl mem8, cl d2h mm-010-xxx vector rcl mreg16/32, cl d3h 11-010-xxx vector rcl mem16/32, cl d3h mm-010-xxx vector rcr mreg8, imm8 c0h 11-011-xxx vector rcr mem8, imm8 c0h mm-011-xxx vector rcr mreg16/32, imm8 c1h 11-011-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 67 rcr mem16/32, imm8 c1h mm-011-xxx vector rcr mreg8, 1 d0h 11-011-xxx vector rcr mem8, 1 d0h mm-011-xxx vector rcr mreg16/32, 1 d1h 11-011-xxx vector rcr mem16/32, 1 d1h mm-011-xxx vector rcr mreg8, cl d2h 11-011-xxx vector rcr mem8, cl d2h mm-011-xxx vector rcr mreg16/32, cl d3h 11-011-xxx vector rcr mem16/32, cl d3h mm-011-xxx vector ret near imm16 c2h vector ret near c3h vector ret far imm16 cah vector ret far cbh vector rol mreg8, imm8 c0h 11-000-xxx vector rol mem8, imm8 c0h mm-000-xxx vector rol mreg16/32, imm8 c1h 11-000-xxx vector rol mem16/32, imm8 c1h mm-000-xxx vector rol mreg8, 1 d0h 11-000-xxx vector rol mem8, 1 d0h mm-000-xxx vector rol mreg16/32, 1 d1h 11-000-xxx vector rol mem16/32, 1 d1h mm-000-xxx vector rol mreg8, cl d2h 11-000-xxx vector rol mem8, cl d2h mm-000-xxx vector rol mreg16/32, cl d3h 11-000-xxx vector rol mem16/32, cl d3h mm-000-xxx vector ror mreg8, imm8 c0h 11-001-xxx vector ror mem8, imm8 c0h mm-001-xxx vector ror mreg16/32, imm8 c1h 11-001-xxx vector ror mem16/32, imm8 c1h mm-001-xxx vector ror mreg8, 1 d0h 11-001-xxx vector ror mem8, 1 d0h mm-001-xxx vector ror mreg16/32, 1 d1h 11-001-xxx vector ror mem16/32, 1 d1h mm-001-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 68 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 ror mreg8, cl d2h 11-001-xxx vector ror mem8, cl d2h mm-001-xxx vector ror mreg16/32, cl d3h 11-001-xxx vector ror mem16/32, cl d3h mm-001-xxx vector sahf 9eh vector sar mreg8, imm8 c0h 11-111-xxx short alux sar mem8, imm8 c0h mm-111-xxx vector sar mreg16/32, imm8 c1h 11-111-xxx short alu sar mem16/32, imm8 c1h mm-111-xxx vector sar mreg8, 1 d0h 11-111-xxx short alux sar mem8, 1 d0h mm-111-xxx vector sar mreg16/32, 1 d1h 11-111-xxx short alu sar mem16/32, 1 d1h mm-111-xxx vector sar mreg8, cl d2h 11-111-xxx short alux sar mem8, cl d2h mm-111-xxx vector sar mreg16/32, cl d3h 11-111-xxx short alu sar mem16/32, cl d3h mm-111-xxx vector sbb mreg8, reg8 18h 11-xxx-xxx vector sbb mem8, reg8 18h mm-xxx-xxx vector sbb mreg16/32, reg16/32 19h 11-xxx-xxx vector sbb mem16/32, reg16/32 19h mm-xxx-xxx vector sbb reg8, mreg8 1ah 11-xxx-xxx vector sbb reg8, mem8 1ah mm-xxx-xxx vector sbb reg16/32, mreg16/32 1bh 11-xxx-xxx vector sbb reg16/32, mem16/32 1bh mm-xxx-xxx vector sbb al, imm8 1ch vector sbb eax, imm16/32 1dh vector sbb mreg8, imm8 80h 11-011-xxx vector sbb mem8, imm8 80h mm-011-xxx vector sbb mreg16/32, imm16/32 81h 11-011-xxx vector sbb mem16/32, imm16/32 81h mm-011-xxx vector sbb mreg16/32, imm8 (signed ext.) 83h 11-011-xxx vector sbb mem16/32, imm8 (signed ext.) 83h mm-011-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 69 scasb al, mem8 aeh vector scasw ax, mem16 afh vector scasd eax, mem32 afh vector seto mreg8 0fh 90h 11-xxx-xxx vector seto mem8 0fh 90h mm-xxx-xxx vector setno mreg8 0fh 91h 11-xxx-xxx vector setno mem8 0fh 91h mm-xxx-xxx vector setb/setnae mreg8 0fh 92h 11-xxx-xxx vector setb/setnae mem8 0fh 92h mm-xxx-xxx vector setnb/setae mreg8 0fh 93h 11-xxx-xxx vector setnb/setae mem8 0fh 93h mm-xxx-xxx vector setz/sete mreg8 0fh 94h 11-xxx-xxx vector setz/sete mem8 0fh 94h mm-xxx-xxx vector setnz/setne mreg8 0fh 95h 11-xxx-xxx vector setnz/setne mem8 0fh 95h mm-xxx-xxx vector setbe/setna mreg8 0fh 96h 11-xxx-xxx vector setbe/setna mem8 0fh 96h mm-xxx-xxx vector setnbe/seta mreg8 0fh 97h 11-xxx-xxx vector setnbe/seta mem8 0fh 97h mm-xxx-xxx vector sets mreg8 0fh 98h 11-xxx-xxx vector sets mem8 0fh 98h mm-xxx-xxx vector setns mreg8 0fh 99h 11-xxx-xxx vector setns mem8 0fh 99h mm-xxx-xxx vector setp/setpe mreg8 0fh 9ah 11-xxx-xxx vector setp/setpe mem8 0fh 9ah mm-xxx-xxx vector setnp/setpo mreg8 0fh 9bh 11-xxx-xxx vector setnp/setpo mem8 0fh 9bh mm-xxx-xxx vector setl/setnge mreg8 0fh 9ch 11-xxx-xxx vector setl/setnge mem8 0fh 9ch mm-xxx-xxx vector setnl/setge mreg8 0fh 9dh 11-xxx-xxx vector setnl/setge mem8 0fh 9dh mm-xxx-xxx vector setle/setng mreg8 0fh 9eh 11-xxx-xxx vector setle/setng mem8 0fh 9eh mm-xxx-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 70 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 setnle/setg mreg8 0fh 9fh 11-xxx-xxx vector setnle/setg mem8 0fh 9fh mm-xxx-xxx vector sgdt mem48 0fh 01h mm-000-xxx vector sidt mem48 0fh 01h mm-001-xxx vector shl/sal mreg8, imm8 c0h 11-100-xxx short alux shl/sal mem8, imm8 c0h mm-100-xxx vector shl/sal mreg16/32, imm8 c1h 11-100-xxx short alu shl/sal mem16/32, imm8 c1h mm-100-xxx vector shl/sal mreg8, 1 d0h 11-100-xxx short alux shl/sal mem8, 1 d0h mm-100-xxx vector shl/sal mreg16/32, 1 d1h 11-100-xxx short alu shl/sal mem16/32, 1 d1h mm-100-xxx vector shl/sal mreg8, cl d2h 11-100-xxx short alux shl/sal mem8, cl d2h mm-100-xxx vector shl/sal mreg16/32, cl d3h 11-100-xxx short alu shl/sal mem16/32, cl d3h mm-100-xxx vector shr mreg8, imm8 c0h 11-101-xxx short alux shr mem8, imm8 c0h mm-101-xxx vector shr mreg16/32, imm8 c1h 11-101-xxx short alu shr mem16/32, imm8 c1h mm-101-xxx vector shr mreg8, 1 d0h 11-101-xxx short alux shr mem8, 1 d0h mm-101-xxx vector shr mreg16/32, 1 d1h 11-101-xxx short alu shr mem16/32, 1 d1h mm-101-xxx vector shr mreg8, cl d2h 11-101-xxx short alux shr mem8, cl d2h mm-101-xxx vector shr mreg16/32, cl d3h 11-101-xxx short alu shr mem16/32, cl d3h mm-101-xxx vector shld mreg16/32, reg16/32, imm8 0fh a4h 11-xxx-xxx vector shld mem16/32, reg16/32, imm8 0fh a4h mm-xxx-xxx vector shld mreg16/32, reg16/32, cl 0fh a5h 11-xxx-xxx vector shld mem16/32, reg16/32, cl 0fh a5h mm-xxx-xxx vector shrd mreg16/32, reg16/32, imm8 0fh ach 11-xxx-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 71 shrd mem16/32, reg16/32, imm8 0fh ach mm-xxx-xxx vector shrd mreg16/32, reg16/32, cl 0fh adh 11-xxx-xxx vector shrd mem16/32, reg16/32, cl 0fh adh mm-xxx-xxx vector sldt mreg16 0fh 00h 11-000-xxx vector sldt mem16 0fh 00h mm-000-xxx vector smsw mreg16 0fh 01h 11-100-xxx vector smsw mem16 0fh 01h mm-100-xxx vector stc f9h vector std fdh vector sti fbh vector stosb mem8, al aah long store, alux stosw mem16, ax abh long store, alux stosd mem32, eax abh long store, alux str mreg16 0fh 00h 11-001-xxx vector str mem16 0fh 00h mm-001-xxx vector sub mreg8, reg8 28h 11-xxx-xxx short alux sub mem8, reg8 28h mm-xxx-xxx long load, alux, store sub mreg16/32, reg16/32 29h 11-xxx-xxx short alu sub mem16/32, reg16/32 29h mm-xxx-xxx long load, alu, store sub reg8, mreg8 2ah 11-xxx-xxx short alux sub reg8, mem8 2ah mm-xxx-xxx short load, alux sub reg16/32, mreg16/32 2bh 11-xxx-xxx short alu sub reg16/32, mem16/32 2bh mm-xxx-xxx short load, alu sub al, imm8 2ch short alux sub eax, imm16/32 2dh short alu sub mreg8, imm8 80h 11-101-xxx short alux sub mem8, imm8 80h mm-101-xxx long load, alux, store sub mreg16/32, imm16/32 81h 11-101-xxx short alu sub mem16/32, imm16/32 81h mm-101-xxx long load, alu, store sub mreg16/32, imm8 (signed ext.) 83h 11-101-xxx short alux sub mem16/32, imm8 (signed ext.) 83h mm-101-xxx long load, alux, store syscall 0fh 05h vector sysret 0fh 07h vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 72 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 test mreg8, reg8 84h 11-xxx-xxx short alux test mem8, reg8 84h mm-xxx-xxx vector test mreg16/32, reg16/32 85h 11-xxx-xxx short alu test mem16/32, reg16/32 85h mm-xxx-xxx vector test al, imm8 a8h long alux test eax, imm16/32 a9h long alu test mreg8, imm8 f6h 11-000-xxx long alux test mem8, imm8 f6h mm-000-xxx long load, alux test mreg16/32, imm16/32 f7h 11-000-xxx long alu test mem16/32, imm16/32 f7h mm-000-xxx long load, alu verr mreg16 0fh 00h 11-100-xxx vector verr mem16 0fh 00h mm-100-xxx vector verw mreg16 0fh 00h 11-101-xxx vector verw mem16 0fh 00h mm-101-xxx vector wait 9bh vector wbinvd 0fh 09h vector xadd mreg8, reg8 0fh c0h 11-100-xxx vector xadd mem8, reg8 0fh c0h mm-100-xxx vector xadd mreg16/32, reg16/32 0fh c1h 11-101-xxx vector xadd mem16/32, reg16/32 0fh c1h mm-101-xxx vector xchg reg8, mreg8 86h 11-xxx-xxx vector xchg reg8, mem8 86h mm-xxx-xxx vector xchg reg16/32, mreg16/32 87h 11-xxx-xxx vector xchg reg16/32, mem16/32 87h mm-xxx-xxx vector xchg eax, eax 90h short limm xchg eax, ecx 91h long alu, alu, alu xchg eax, edx 92h long alu, alu, alu xchg eax, ebx 93h long alu, alu, alu xchg eax, esp 94h long alu, alu, alu xchg eax, ebp 95h long alu, alu, alu xchg eax, esi 96h long alu, alu, alu xchg eax, edi 97h long alu, alu, alu xlat d7h vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 73 xor mreg8, reg8 30h 11-xxx-xxx short alux xor mem8, reg8 30h mm-xxx-xxx long load, alux, store xor mreg16/32, reg16/32 31h 11-xxx-xxx short alu xor mem16/32, reg16/32 31h mm-xxx-xxx long load, alu, store xor reg8, mreg8 32h 11-xxx-xxx short alux xor reg8, mem8 32h mm-xxx-xxx short load, alux xor reg16/32, mreg16/32 33h 11-xxx-xxx short alu xor reg16/32, mem16/32 33h mm-xxx-xxx short load, alu xor al, imm8 34h short alux xor eax, imm16/32 35h short alu xor mreg8, imm8 80h 11-110-xxx short alux xor mem8, imm8 80h mm-110-xxx long load, alux, store xor mreg16/32, imm16/32 81h 11-110-xxx short alu xor mem16/32, imm16/32 81h mm-110-xxx long load, alu, store xor mreg16/32, imm8 (signed ext.) 83h 11-110-xxx short alux xor mem16/32, imm8 (signed ext.) 83h mm-110-xxx long load, alux, store table 13. floating-point instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 operations note f2xm1 d9h f0h short float fabs d9h f1h short float fadd st(0), st(i) d8h 11-000-xxx short float * fadd st(0), mem32real d8h mm-000-xxx short fload, float fadd st(i), st(0) dch 11-000-xxx short float * fadd st(0), mem64real dch mm-000-xxx short fload, float faddp st(i), st(0) deh 11-000-xxx short float * fbld dfh mm-100-xxx vector fbstp dfh mm-110-xxx vector fchs d9h e0h short float fclex dbh e2h vector note: * the last three bits of the modr/m byte select the stack entry st(i). table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations 74 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 fcom st(0), st(i) d8h 11-010-xxx short float * fcom st(0), mem32real d8h mm-010-xxx short fload, float fcom st(0), mem64real dch mm-010-xxx short fload, float fcomp st(0), st(i) d8h 11-011-xxx short float * fcomp st(0), mem32real d8h mm-011-xxx short fload, float fcomp st(0), mem64real dch mm-011-xxx short fload, float fcompp deh d9h 11-011-001 short float fcos d9h ffh short float fdecstp d9h f6h short float fdiv st(0), st(i) (single precision) d8h 11-110-xxx short float * fdiv st(0), st(i) (double precision) d8h 11-110-xxx short float * fdiv st(0), st(i) (extended precision) d8h 11-110-xxx short float * fdiv st(i), st(0) (single precision) dch 11-111-xxx short float * fdiv st(i), st(0) (double precision) dch 11-111-xxx short float * fdiv st(i), st(0) (extended precision) dch 11-111-xxx short float * fdiv st(0), mem32real d8h mm-110-xxx short fload, float fdiv st(0), mem64real dch mm-110-xxx short fload, float fdivp st(0), st(i) deh 11-111-xxx short float * fdivr st(0), st(i) d8h 11-110-xxx short float * fdivr st(i), st(0) dch 11-111-xxx short float * fdivr st(0), mem32real d8h mm-111-xxx short fload, float fdivr st(0), mem64real dch mm-111-xxx short fload, float fdivrp st(i), st(0) deh 11-110-xxx short float * ffree st(i) ddh 11-000-xxx short float * fiadd st(0), mem32int dah mm-000-xxx short fload, float fiadd st(0), mem16int deh mm-000-xxx short fload, float ficom st(0), mem32int dah mm-010-xxx short fload, float ficom st(0), mem16int deh mm-010-xxx short fload, float ficomp st(0), mem32int dah mm-011-xxx short fload, float ficomp st(0), mem16int deh mm-011-xxx short fload, float fidiv st(0), mem32int dah mm-110-xxx short fload, float table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations note note: * the last three bits of the modr/m byte select the stack entry st(i). 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 75 fidiv st(0), mem16int deh mm-110-xxx short fload, float fidivr st(0), mem32int dah mm-111-xxx short fload, float fidivr st(0), mem16int deh mm-111-xxx short fload, float fild mem16int dfh mm-000-xxx short fload, float fild mem32int dbh mm-000-xxx short fload, float fild mem64int dfh mm-101-xxx short fload, float fimul st(0), mem32int dah mm-001-xxx short fload, float fimul st(0), mem16int deh mm-001-xxx short fload, float fincstp d9h f7h short finit dbh e3h vector fist mem16int dfh mm-010-xxx short fload, float fist mem32int dbh mm-010-xxx short fload, float fistp mem16int dfh mm-011-xxx short fload, float fistp mem32int dbh mm-011-xxx short fload, float fistp mem64int dfh mm-111-xxx short fload, float fisub st(0), mem32int dah mm-100-xxx short fload, float fisub st(0), mem16int deh mm-100-xxx short fload, float fisubr st(0), mem32int dah mm-101-xxx short fload, float fisubr st(0), mem16int deh mm-101-xxx short fload, float fld st(i) d9h 11-000-xxx short fload, float * fld mem32real d9h mm-000-xxx short fload, float fld mem64real ddh mm-000-xxx short fload, float fld mem80real dbh mm-101-xxx vector fld1 d9h e8h short fload, float fldcw d9h mm-101-xxx vector fldenv d9h mm-100-xxx short fload, float fldl2e d9h eah short float fldl2t d9h e9h short float fldlg2 d9h ech short float fldln2 d9h edh short float fldpi d9h ebh short float table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations note note: * the last three bits of the modr/m byte select the stack entry st(i). 76 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 fldz d9h eeh short float fmul st(0), st(i) d8h 11-001-xxx short float * fmul st(i), st(0) dch 11-001-xxx short float * fmul st(0), mem32real d8h mm-001-xxx short fload, float fmul st(0), mem64real dch mm-001-xxx short fload, float fmulp st(0), st(i) deh 11-001-xxx short float * fnop d9h d0h short float fpatan d9h f3h short float fprem d9h f8h short float fprem1 d9h f5h short float fptan d9h f2h vector frndint d9h fch short float frstor ddh mm-100-xxx vector fsave ddh mm-110-xxx vector fscale d9h fdh short float fsin d9h feh short float fsincos d9h fbh vector fsqrt (single precision) d9h fah short float fsqrt (double precision) d9h fah short float fsqrt (extended precision) d9h fah short float fst mem32real d9h mm-010-xxx short fstore fst mem64real ddh mm-010-xxx short fstore fst st(i) ddh 11-010-xxx short fstore * fstcw d9h mm-111-xxx vector fstenv d9h mm-110-xxx vector fstp mem32real d9h mm-011-xxx short fstore fstp mem64real ddh mm-011-xxx short fstore fstp mem80real d9h mm-111-xxx vector fstp st(i) ddh 11-011-xxx short float * fstsw ax dfh e0h vector fstsw mem16 ddh mm-111-xxx vector table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations note note: * the last three bits of the modr/m byte select the stack entry st(i). 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 77 fsub st(0), mem32real d8h mm-100-xxx short fload, float fsub st(0), mem64real dch mm-100-xxx short fload, float fsub st(0), st(i) d8h 11-100-xxx short float * fsub st(i), st(0) dch 11-101-xxx short float * fsubp st(0), st(i) deh 11-101-xxx short float * fsubr st(0), mem32real d8h mm-101-xxx short fload, float fsubr st(0), mem64real dch mm-101-xxx short fload, float fsubr st(0), st(i) d8h 11-100-xxx short float * fsubr st(i), st(0) dch 11-101-xxx short float * fsubrp st(i), st(0) deh 11-100-xxx short float * ftst d9h e4h short float fucom ddh 11-100-xxx short float fucomp ddh 11-101-xxx short float fucompp dah e9h short float fxam d9h e5h short float fxch d9h 11-001-xxx short float fxtract d9h f4h vector fyl2x d9h f1h short float fyl2xp1 d9h f9h short float fwait 9bh vector table 14. mmx? instructions instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations note emms 0fh 77h vector movd mmreg, mreg32 0fh 6eh 11-xxx-xxx short meu ** movd mmreg, mem32 0fh 6eh mm-xxx-xxx short mload movd mreg32, mmreg 0fh 7eh 11-xxx-xxx short mstore, load ** movd mem32, mmreg 0fh 7eh mm-xxx-xxx short mstore movq mmreg1, mmreg2 0fh 6fh 11-xxx-xxx short meu note: ** bits 2, 1, and 0 of the modr/m byte select the integer register. table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations note note: * the last three bits of the modr/m byte select the stack entry st(i). 78 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 movq mmreg, mem64 0fh 6fh mm-xxx-xxx short mload movq mmreg2, mmreg1 0fh 7fh 11-xxx-xxx short meu movq mem64, mmreg 0fh 7fh mm-xxx-xxx short mstore packssdw mmreg1, mmreg2 0fh 6bh 11-xxx-xxx short meu packssdw mmreg, mem64 0fh 6bh mm-xxx-xxx short mload, meu packsswb mmreg1, mmreg2 0fh 63h 11-xxx-xxx short meu packsswb mmreg, mem64 0fh 63h mm-xxx-xxx short mload, meu packuswb mmreg1, mmreg2 0fh 67h 11-xxx-xxx short meu packuswb mmreg, mem64 0fh 67h mm-xxx-xxx short mload, meu paddb mmreg1, mmreg2 0fh fch 11-xxx-xxx short meu paddb mmreg, mem64 0fh fch mm-xxx-xxx short mload, meu paddd mmreg1, mmreg2 0fh feh 11-xxx-xxx short meu paddd mmreg, mem64 0fh feh mm-xxx-xxx short mload, meu paddsb mmreg1, mmreg2 0fh ech 11-xxx-xxx short meu paddsb mmreg, mem64 0fh ech mm-xxx-xxx short mload, meu paddsw mmreg1, mmreg2 0fh edh 11-xxx-xxx short meu paddsw mmreg, mem64 0fh edh mm-xxx-xxx short mload, meu paddusb mmreg1, mmreg2 0fh dch 11-xxx-xxx short meu paddusb mmreg, mem64 0fh dch mm-xxx-xxx short mload, meu paddusw mmreg1, mmreg2 0fh ddh 11-xxx-xxx short meu paddusw mmreg, mem64 0fh ddh mm-xxx-xxx short mload, meu paddw mmreg1, mmreg2 0fh fdh 11-xxx-xxx short meu paddw mmreg, mem64 0fh fdh mm-xxx-xxx short mload, meu pand mmreg1, mmreg2 0fh dbh 11-xxx-xxx short meu pand mmreg, mem64 0fh dbh mm-xxx-xxx short mload, meu pandn mmreg1, mmreg2 0fh dfh 11-xxx-xxx short meu pandn mmreg, mem64 0fh dfh mm-xxx-xxx short mload, meu pcmpeqb mmreg1, mmreg2 0fh 74h 11-xxx-xxx short meu pcmpeqb mmreg, mem64 0fh 74h mm-xxx-xxx short mload, meu pcmpeqd mmreg1, mmreg2 0fh 76h 11-xxx-xxx short meu pcmpeqd mmreg, mem64 0fh 76h mm-xxx-xxx short mload, meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations note note: ** bits 2, 1, and 0 of the modr/m byte select the integer register. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 79 pcmpeqw mmreg1, mmreg2 0fh 75h 11-xxx-xxx short meu pcmpeqw mmreg, mem64 0fh 75h mm-xxx-xxx short mload, meu pcmpgtb mmreg1, mmreg2 0fh 64h 11-xxx-xxx short meu pcmpgtb mmreg, mem64 0fh 64h mm-xxx-xxx short mload, meu pcmpgtd mmreg1, mmreg2 0fh 66h 11-xxx-xxx short meu pcmpgtd mmreg, mem64 0fh 66h mm-xxx-xxx short mload, meu pcmpgtw mmreg1, mmreg2 0fh 65h 11-xxx-xxx short meu pcmpgtw mmreg, mem64 0fh 65h mm-xxx-xxx short mload, meu pmaddwd mmreg1, mmreg2 0fh f5h 11-xxx-xxx short meu pmaddwd mmreg, mem64 0fh f5h mm-xxx-xxx short mload, meu pmulhw mmreg1, mmreg2 0fh e5h 11-xxx-xxx short meu pmulhw mmreg, mem64 0fh e5h mm-xxx-xxx short mload, meu pmullw mmreg1, mmreg2 0fh d5h 11-xxx-xxx short meu pmullw mmreg, mem64 0fh d5h mm-xxx-xxx short mload, meu por mmreg1, mmreg2 0fh ebh 11-xxx-xxx short meu por mmreg, mem64 0fh ebh mm-xxx-xxx short mload, meu pslld mmreg1, mmreg2 0fh f2h 11-xxx-xxx short meu pslld mmreg, mem64 0fh f2h mm-xxx-xxx short mload, meu pslld mmreg, imm8 0fh 72h 11-110-xxx short meu psllq mmreg1, mmreg2 0fh f3h 11-xxx-xxx short meu psllq mmreg, mem64 0fh f3h mm-xxx-xxx short mload, meu psllq mmreg, imm8 0fh 73h 11-110-xxx short meu psllw mmreg1, mmreg2 0fh f1h 11-xxx-xxx short meu psllw mmreg, mem64 0fh f1h mm-xxx-xxx short mload, meu psllw mmreg, imm8 0fh 71h 11-110-xxx short meu psrad mmreg1, mmreg2 0fh e2h 11-xxx-xxx short meu psrad mmreg, mem64 0fh e2h mm-xxx-xxx short mload, meu psrad mmreg, imm8 0fh 72h 11-100-xxx short meu psraw mmreg1, mmreg2 0fh e1h 11-xxx-xxx short meu psraw mmreg, mem64 0fh e1h mm-xxx-xxx short mload, meu psraw mmreg, imm8 0fh 71h 11-100-xxx short meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations note note: ** bits 2, 1, and 0 of the modr/m byte select the integer register. 80 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 psrld mmreg1, mmreg2 0fh d2h 11-xxx-xxx short meu psrld mmreg, mem64 0fh d2h mm-xxx-xxx short mload, meu psrld mmreg, imm8 0fh 72h 11-010-xxx short meu psrlq mmreg1, mmreg2 0fh d3h 11-xxx-xxx short meu psrlq mmreg, mem64 0fh d3h mm-xxx-xxx short mload, meu psrlq mmreg, imm8 0fh 73h 11-010-xxx short meu psrlw mmreg1, mmreg2 0fh d1h 11-xxx-xxx short meu psrlw mmreg, mem64 0fh d1h mm-xxx-xxx short mload, meu psrlw mmreg, imm8 0fh 71h 11-010-xxx short meu psubb mmreg1, mmreg2 0fh f8h 11-xxx-xxx short meu psubb mmreg, mem64 0fh f8h mm-xxx-xxx short mload, meu psubd mmreg1, mmreg2 0fh fah 11-xxx-xxx short meu psubd mmreg, mem64 0fh fah mm-xxx-xxx short mload, meu psubsb mmreg1, mmreg2 0fh e8h 11-xxx-xxx short meu psubsb mmreg, mem64 0fh e8h mm-xxx-xxx short mload, meu psubsw mmreg1, mmreg2 0fh e9h 11-xxx-xxx short meu psubsw mmreg, mem64 0fh e9h mm-xxx-xxx short mload, meu psubusb mmreg1, mmreg2 0fh d8h 11-xxx-xxx short meu psubusb mmreg, mem64 0fh d8h mm-xxx-xxx short mload, meu psubusw mmreg1, mmreg2 0fh d9h 11-xxx-xxx short meu psubusw mmreg, mem64 0fh d9h mm-xxx-xxx short mload, meu psubw mmreg1, mmreg2 0fh f9h 11-xxx-xxx short meu psubw mmreg, mem64 0fh f9h mm-xxx-xxx short mload, meu punpckhbw mmreg1, mmreg2 0fh 68h 11-xxx-xxx short meu punpckhbw mmreg, mem64 0fh 68h mm-xxx-xxx short mload, meu punpckhdq mmreg1, mmreg2 0fh 6ah 11-xxx-xxx short meu punpckhdq mmreg, mem64 0fh 6ah mm-xxx-xxx short mload, meu punpckhwd mmreg1, mmreg2 0fh 69h 11-xxx-xxx short meu punpckhwd mmreg, mem64 0fh 69h mm-xxx-xxx short mload, meu punpcklbw mmreg1, mmreg2 0fh 60h 11-xxx-xxx short meu punpcklbw mmreg, mem64 0fh 60h mm-xxx-xxx short mload, meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations note note: ** bits 2, 1, and 0 of the modr/m byte select the integer register. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 3 software environment 81 punpckldq mmreg1, mmreg2 0fh 62h 11-xxx-xxx short meu punpckldq mmreg, mem64 0fh 62h mm-xxx-xxx short mload, meu punpcklwd mmreg1, mmreg2 0fh 61h 11-xxx-xxx short meu punpcklwd mmreg, mem64 0fh 61h mm-xxx-xxx short mload, meu pxor mmreg1, mmreg2 0fh efh 11-xxx-xxx short meu pxor mmreg, mem64 0fh efh mm-xxx-xxx short mload, meu table 15. 3dnow!? instructions instruction mnemonic prefix byte(s) opcode byte modr/m byte decode type risc86 operations note femms 0fh 0eh vector pavgusb mmreg1, mmreg2 0fh, 0fh bfh 11-xxx-xxx short meu pavgusb mmreg, mem64 0fh, 0fh bfh mm-xxx-xxx short mload, meu pf2id mmreg1, mmreg2 0fh, 0fh 1dh 11-xxx-xxx short meu pf2id mmreg, mem64 0fh, 0fh 1dh mm-xxx-xxx short mload, meu pfacc mmreg1, mmreg2 0fh, 0fh aeh 11-xxx-xxx short meu pfacc mmreg, mem64 0fh, 0fh aeh mm-xxx-xxx short mload, meu pfadd mmreg1, mmreg2 0fh, 0fh 9eh 11-xxx-xxx short meu pfadd mmreg, mem64 0fh, 0fh 9eh mm-xxx-xxx short mload, meu pfcmpeq mmreg1, mmreg2 0fh, 0fh b0h 11-xxx-xxx short meu pfcmpeq mmreg, mem64 0fh, 0fh b0h mm-xxx-xxx short mload, meu pfcmpge mmreg1, mmreg2 0fh, 0fh 90h 11-xxx-xxx short meu pfcmpge mmreg, mem64 0fh, 0fh 90h mm-xxx-xxx short mload, meu pfcmpgt mmreg1, mmreg2 0fh, 0fh a0h 11-xxx-xxx short meu pfcmpgt mmreg, mem64 0fh, 0fh a0h mm-xxx-xxx short mload, meu pfmax mmreg1, mmreg2 0fh, 0fh a4h 11-xxx-xxx short meu pfmax mmreg, mem64 0fh, 0fh a4h mm-xxx-xxx short mload, meu pfmin mmreg1, mmreg2 0fh, 0fh 94h 11-xxx-xxx short meu notes: 1. for prefetch and prefetchw, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. prefetchw will be implemented in a future k86 processor. on the amd-k6- iii processor, this instruction performs in the same manner as the prefetch instruction. table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations note note: ** bits 2, 1, and 0 of the modr/m byte select the integer register. 82 software environment chapter 3 amd-k6 ? - iii processor data sheet 21918b/0october 1999 pfmin mmreg, mem64 0fh, 0fh 94h mm-xxx-xxx short mload, meu pfmul mmreg1, mmreg2 0fh, 0fh b4h 11-xxx-xxx short meu pfmul mmreg, mem64 0fh, 0fh b4h mm-xxx-xxx short mload, meu pfrcp mmreg1, mmreg2 0fh, 0fh 96h 11-xxx-xxx short meu pfrcp mmreg, mem64 0fh, 0fh 96h mm-xxx-xxx short mload, meu pfrcpit1 mmreg1, mmreg2 0fh, 0fh a6h 11-xxx-xxx short meu pfrcpit1 mmreg, mem64 0fh, 0fh a6h mm-xxx-xxx short mload, meu pfrcpit2 mmreg1, mmreg2 0fh, 0fh b6h 11-xxx-xxx short meu pfrcpit2 mmreg, mem64 0fh, 0fh b6h mm-xxx-xxx short mload, meu pfrsqit1 mmreg1, mmreg2 0fh, 0fh a7h 11-xxx-xxx short meu pfrsqit1 mmreg, mem64 0fh, 0fh a7h mm-xxx-xxx short mload, meu pfrsqrt mmreg1, mmreg2 0fh, 0fh 97h 11-xxx-xxx short meu pfrsqrt mmreg, mem64 0fh, 0fh 97h mm-xxx-xxx short mload, meu pfsub mmreg1, mmreg2 0fh, 0fh 9ah 11-xxx-xxx short meu pfsub mmreg, mem64 0fh, 0fh 9ah mm-xxx-xxx short mload, meu pfsubr mmreg1, mmreg2 0fh, 0fh aah 11-xxx-xxx short meu pfsubr mmreg, mem64 0fh, 0fh aah mm-xxx-xxx short mload, meu pi2fd mmreg1, mmreg2 0fh, 0fh 0dh 11-xxx-xxx short meu pi2fd mmreg, mem64 0fh, 0fh 0dh mm-xxx-xxx short mload, meu pmulhrw mmreg1, mmreg2 0fh, 0fh b7h 11-xxx-xxx short meu pmulhrw mmreg1, mem64 0fh, 0fh b7h mm-xxx-xxx short mload, meu prefetch mem8 0fh 0dh mm-000-xxx vector load 1 prefetchw mem8 0fh 0dh mm-001-xxx vector load 1, 2 table 15. 3dnow!? instructions (continued) instruction mnemonic prefix byte(s) opcode byte modr/m byte decode type risc86 operations note notes: 1. for prefetch and prefetchw, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. prefetchw will be implemented in a future k86 processor. on the amd-k6- iii processor, this instruction performs in the same manner as the prefetch instruction. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 83 4 signal descriptions 4.1 signal terminology the following terminology is used in this chapter: n driven the processor actively pulls the signal up to the high-voltage state or pulls the signal down to the low-voltage state. n floated the the signal is not being driven by the processor (high-impedance state), which allows another device to drive this signal. n asserted for all active-high signals, the term asserted means the signal is in the high-voltage state. for all active-low signals, the term asserted means the signal is in the low-voltage state. n negated for all active-high signals, the term negated means the signal is in the low-voltage state. for all active-low signals, the term negated means the signal is in the high-voltage state. n sampled the processor has measured the state of a signal at predefined points in time and will take the appropriate action based on the state of the signal. if a signal is not sampled by the processor, its assertion or negation has no effect on the operation of the processor. figure 53 on page 84 shows the signals grouped by function. the arrows in the figure indicate the direction of the signal, either into or out of the processor. signals with double-headed arrows are bidirectional. signals with pound signs (#) are active low. 84 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 53. logic symbol diagram a20m# a[31:3] ap ads# adsc# apchk# be[7:0]# ahold boff# breq hlda hold d/c# ewbe# lock# m/io# na# scyc w/r# cache# ken# pcd pwt wb/wt# clock bus arbitration clk bf[2:0] tck tdi tdo tms trst# brdy# brdyc# d[63:0] dp[7:0] pchk# eads# hit# hitm# inv ferr# ignne# flush# init intr nmi reset smi# smiact# stpclk# jtag test data and data parity inquire cycles floating-point error handling external interrupts, smm, reset and initialization address and address parity cycle definition and control cache control amd-k6 ? - iii processor voltage detection vcc2det vcc2h/l# 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 85 4.2 a20m# (address bit 20 mask) input summary a20m# is used to simulate the behavior of the 8086 when running in real mode. the assertion of a20m# causes the processor to force bit 20 of the physical address to 0 prior to accessing the caches or driving out a memory bus cycle. the clearing of address bit 20 maps addresses that extend above the 8086 1-mbyte limit to below 1 mbyte. sampled the processor samples a20m# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. the following list explains the effects of the processor sampling a20m# asserted under various conditions: n inquire cycles and writeback cycles are not affected by the state of a20m#. n the assertion of a20m# in system management mode (smm) is ignored. n when a20m# is sampled asserted in protected mode, it causes unpredictable processor operation. a20m# is only defined in real mode. n to ensure that a20m# is recognized before the first ads# occurs following the negation of reset, a20m# must be sampled asserted on the same clock edge that reset is sampled negated or on one of the two subsequent clock edges. n to ensure a20m# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts a20m# and the targeted instruction. 86 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.3 a[31:3] (address bus) a[31:5] bidirectional, a[4:3] output summary a[31:3] contain the physical address for the current bus cycle. the processor drives addresses on a[31:3] during memory and i/o cycles, and cycle definition information during special bus cycles. the processor samples addresses on a[31:5] during inquire cycles. driven, sampled, and floated as outputs: a[31:3] are driven valid off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. a[31:3] are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive the address bus while the bus is idle. as inputs: the processor samples a[31:5] during inquire cycles on the clock edge on which eads# is sampled asserted. even though a4 and a3 are not used during the inquire cycle, they must be driven to a valid state and must meet the same timings as a[31:5]. a[31:3] are floated off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving a[31:3] off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 87 4.4 ads# (address strobe) output summary the assertion of ads# indicates the beginning of a new bus cycle. the address bus and all cycle definition signals corresponding to this bus cycle are driven valid off the same clock edge as ads#. driven and floated ads# is asserted for one clock at the beginning of each bus cycle. for non-pipelined cycles, ads# can be asserted as early as the clock edge after the clock edge on which the last expected brdy# of the cycle is sampled asserted, resulting in a single idle state between cycles. for pipelined cycles if the processor is prepared to start a new cycle, ads# can be asserted as early as one clock edge after na# is sampled asserted. if ahold is sampled asserted, ads# is only driven in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. the processor floats ads# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 4.5 adsc# (address strobe copy) output summary adsc# has the identical function and timing as ads#. in the event ads# becomes too heavily loaded due to a large fanout in a system, adsc# can be used to split the load across two outputs, which can improve system timing. 88 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.6 ahold (address hold) input summary ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this allows a bus cycle that is in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. if ahold is sampled asserted, ads# is only asserted in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. sampled the processor samples ahold on every clock edge. ahold is recognized while init and reset are sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 89 4.7 ap (address parity) bidirectional summary ap contains the even parity bit for cache line addresses driven and sampled on a[31:5]. even parity means that the total number of 1 bits on ap and a[31:5] is even. (a4 and a3 are not used for the generation or checking of address parity because these bits are not required to address a cache line.) ap is driven by the processor during processor-initiated cycles and is sampled by the processor during inquire cycles. if ap does not reflect even parity during an inquire cycle, the processor asserts apchk# to indicate an address bus parity check. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. driven, sampled, and floated as an output: the processor drives ap valid off the clock edge on which ads# is asserted until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. ap is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive ap while the bus is idle. as an input: the processor samples ap during inquire cycles on the clock edge on which eads# is sampled asserted. the processor floats ap off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving ap off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda. 90 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.8 apchk# (address parity check) output summary if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. the processor is designed so that apchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven apchk# is driven valid off the clock edge after the clock edge on which the processor samples eads# asserted. it is negated off the next clock edge. apchk# is always driven except in the tri-state test mode. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 91 4.9 be[7:0]# (byte enables) output summary be[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. the byte enables can be used to derive address bits a[2:0], which are not physically part of the processors address bus. the processor checks and generates valid data parity for the data bytes that are valid as defined by the byte enables. the eight byte enables correspond to the eight bytes of the data bus as follows: the processor expects data to be driven by the system logic on all eight bytes of the data bus during a burst cache-line read cycle, independent of the byte enables that are asserted. the byte enables are also used to distinguish between special bus cycles as defined in table 23 on page 126. driven and floated be[7:0]# are driven off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. be[7:0]# are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor floats be[7:0]# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. unlike the address bus, be[7:0]# are not floated in response to ahold. n be7#: d[63:56] n be3#: d[31:24] n be6#: d[55:48] n be2#: d[23:16] n be5#: d[47:40] n be1#: d[15:8] n be4#: d[39:32] n be0#: d[7:0] 92 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.10 bf[2:0] (bus frequency) inputs, internal pullups summary bf[2:0] determine the internal operating frequency of the processor. the frequency of the clk input signal is multiplied internally by a ratio determined by the state of these signals as defined in table 16. bf[2:0] have weak internal pullups and default to the 3.5 multiplier if left unconnected. table 16. processor-to-bus clock ratios sampled bf[2:0] are sampled during the falling transition of reset. they must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. state of bf[2:0] inputs processor-clock to bus-clock ratio 100b 2.5x 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 93 4.11 boff# (backoff) input summary if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. these signals remain floated until boff# is sampled negated. this allows an alternate bus master or the system to control the bus. when boff# is sampled negated, any processor cycle that was aborted due to the assertion of boff# is restarted from the beginning of the cycle, regardless of the number of transfers that were completed. if boff# is sampled asserted on the same clock edge as brdy# of a bus cycle of any length, then boff# takes precedence over the brdy#. in this case, the cycle is aborted and restarted after boff# is sampled negated. sampled boff# is sampled on every clock edge. the processor floats its bus signals off the clock edge on which boff# is sampled asserted. these signals remain floated until the clock edge on which boff# is sampled negated. boff# is recognized while init and reset are sampled asserted. 94 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.12 brdy# (burst ready) input, internal pullup summary brdy# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the data bus has been latched during a write cycle. if necessary, the system logic can insert bus cycle wait states by negating brdy# until it is ready to continue the data transfer. brdy# is also used to indicate the completion of special bus cycles. sampled brdy# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. brdy# is ignored while the bus is idle. the processor samples the following inputs on the clock edge on which brdy# is sampled asserted: d[63:0], dp[7:0], and ken# during read cycles, ewbe# during write cycles (if not masked off), and wb/wt# during read and write cycles. if na# is sampled asserted prior to brdy#, then ken# and wb/wt# are sampled on the clock edge on which na# is sampled asserted. the number of times the processor expects to sample brdy# asserted depends on the type of bus cycle, as follows: n one time for a single-transfer cycle, a special bus cycle, or each of two cycles in an interrupt acknowledge sequence n four times for a burst cycle (once for each data transfer) brdy# can be held asserted for four consecutive clocks throughout the four transfers of the burst, or it can be negated to insert wait states. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 95 4.13 brdyc# (burst ready copy) input, internal pullup summary brdyc# has the identical function as brdy#. in the event brdy# becomes too heavily loaded due to a large fanout or loading in a system, brdyc# can be used to reduce this loading, which improves timing. sampled brdyc# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. 4.14 breq (bus request) output summary breq is asserted by the processor to request the bus in order to complete an internally pending bus cycle. the system logic can use breq to arbitrate among the bus participants. if the processor does not own the bus, breq is asserted until the processor gains access to the bus in order to begin the pending cycle or until the processor no longer needs to run the pending cycle. if the processor currently owns the bus, breq is asserted with ads#. the processor asserts breq for each assertion of ads# but does not necessarily assert ads# for each assertion of breq. driven breq is asserted off the same clock edge on which ads# is asserted. breq can also be asserted off any clock edge, independent of the assertion of ads#. breq can be negated one clock edge after it is asserted. the processor always drives breq except in the tri-state test mode. 96 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.15 cache# (cacheable access) output summary for reads, cache# is asserted to indicate the cacheability of the current bus cycle. in addition, if the processor samples ken# asserted, which indicates the driven address is cacheable, the cycle is a 32-byte burst read cycle. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if cache# is not asserted, or if ken# is sampled negated during a read cycle, the cycle is not cacheable and defaults to a single-transfer cycle. driven and floated cache# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. cache# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 4.16 clk (clock) input summary the clk signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for tdi, tdo, tms, and trst#). bf[2:0] determine the internal frequency multiplier applied to clk to obtain the processors core operating frequency. see bf[2:0] (bus frequency) on page 92 for a list of the processor-to-bus clock ratios. sampled the clk signal must be stable a minimum of 1.0 ms prior to the negation of reset to ensure the proper operation of the processor. see clk switching characteristics on page 267 for details regarding the clk specifications. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 97 4.17 d/c# (data/code) output summary the processor drives d/c# during a memory bus cycle to indicate whether it is addressing data or executable code. d/c# is also used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 on page 126 for more details. driven and floated d/c# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. d/c# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. d/c# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 98 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.18 d[63:0] (data bus) bidirectional summary d[63:0] represent the processors 64-bit data bus. each of the eight bytes of data that comprise this bus is qualified as valid by its corresponding byte enable. see be[7:0]# (byte enables) on page 91. driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted and d[63:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writebackin which case four, 8-byte transfers occurd[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. if the assertion of ads# represents a pipelined write cycle that follows a read cycle, the processor does not drive d[63:0] until it is certain that contention on the data bus will not occur. in this case, d[63:0] are driven the clock edge after the last expected brdy# of the previous cycle is sampled asserted. as inputs: during read cycles, the processor samples d[63:0] on the clock edge on which brdy# is sampled asserted. the processor always floats d[63:0] except when they are being driven during a write cycle as described above. in addition, d[63:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 99 4.19 dp[7:0] (data parity) bidirectional summary dp[7:0] are even parity bits for each valid byte of dataas defined by be[7:0]#driven and sampled on the d[63:0] data bus. even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is an even number. dp[7:0] are driven by the processor during write cycles and sampled by the processor during read cycles. if the processor detects bad parity on any valid byte of data during a read cycle, pchk# is asserted for one clock beginning the clock edge after brdy# is sampled asserted. the processor does not take an internal exception as the result of detecting a data parity check, and system logic must respond appropriately to the assertion of this signal. the eight data parity bits correspond to the eight bytes of the data bus as follows: for systems that do not support data parity, dp[7:0] should be connected to v cc3 through pullup resistors. driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives dp[7:0] with valid parity one clock edge after the clock edge on which ads# is asserted and dp[7:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writeback, dp[7:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. as inputs: during read cycles, the processor samples dp[7:0] on the clock edge brdy# is sampled asserted. the processor always floats dp[7:0] except when they are being driven during a write cycle as described above. in addition, dp[7:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. n dp7: d[63:56] n dp3: d[31:24] n dp6: d[55:48] n dp2: d[23:16] n dp5: d[47:40] n dp1: d[15:8] n dp4: d[39:32] n dp0: d[7:0] 100 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.20 eads# (external address strobe) input summary system logic asserts eads# during a cache inquire cycle to indicate that the address bus contains a valid address. eads# can only be driven after the system logic has taken control of the address bus by asserting ahold or boff# or by receiving hlda. the processor responds to the sampling of eads# and the address bus by driving hit#, which indicates if the inquired cache line exists in the processors caches, and hitm#, which indicates if it is in the modified state. sampled if ahold or boff# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after ahold or boff# is sampled asserted. if the system logic asserts hold in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after the clock edge hlda is asserted by the processor. eads# is ignored during the following conditions: n one clock edge after the clock edge on which eads# is sampled asserted n two clock edges after the clock edge on which ads# is asserted n when the processor is driving the address bus n when the processor asserts hitm# 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 101 4.21 ewbe# (external write buffer empty) input summary the system logic can negate ewbe# to the processor to indicate that its external write buffers are full and that additional data cannot be stored at this time. this causes the processor to delay the following activities until ewbe# is sampled asserted: n the commitment of write hit cycles to cache lines in the modified state or exclusive state in the processors caches n the decode and execution of an instruction that follows a currently-executing serializing instruction n the assertion or negation of smiact# n the entering of the halt state and the stop grant state negating ewbe# does not prevent the completion of any type of cycle that is currently in progress. sampled the processor samples ewbe# on each clock edge that brdy# is sampled asserted during all memory write cycles (except writeback cycles), i/o write cycles, and special bus cycles. if ewbe# is sampled negated, it is sampled on every clock edge until it is asserted, and then it is ignored until brdy# is sampled asserted in the next write cycle or special cycle. if efer[3] is set to 1, then ewbe# is ignored by the processor. for more information on the efer settings and ewbe#, see ewbe control on page 203. 102 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.22 ferr# (floating-point error) output summary the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. this signal is provided to allow the system logic to handle this exception in a manner consistent with ibm- compatible pc/at systems. see handling floating-point exceptions on page 209 for a system logic implementation that supports floating-point exceptions. the state of the numeric error (ne) bit in cr0 does not affect the ferr# signal. the processor is designed so that ferr# does not glitch, enabling the signal to be used as a clocking source for system logic. driven the processor asserts ferr# on the instruction boundary of the next floating-point instruction, mmx instruction, 3dnow! instruction, or wait instruction that occurs following the floating-point instruction that caused the unmasked floating-point exceptionthat is, ferr# is not asserted at the time the exception occurs. the ignne# signal does not affect the assertion of ferr#. ferr# is negated during the following conditions: n following the successful execution of the floating-point instructions fclex, finit, fsave, and fstenv n under certain circumstances, following the successful execution of the floating-point instructions fldcw, fldenv, and frstor, which load the floating-point status word or the floating-point control word n following the falling transition of reset ferr# is always driven except in the tri-state test mode. see ignne# (ignore numeric exception) on page 106 for more details on floating-point exceptions. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 103 4.23 flush# (cache flush) input summary in response to sampling flush# asserted, the processor writes back any cache lines in the l1 data cache or l2 cache that are in the modified state, invalidates all lines in the l1 and l2 caches, and then executes a flush acknowledge special cycle. see table 23 on page 126 for the bus definition of special cycles. in addition, flush# is sampled when reset is negated to determine if the processor enters the tri-state test mode. if flush# is 0 during the falling transition of reset, the processor enters the tri-state test mode instead of performing the normal reset functions. sampled flush# is sampled and latched as a falling edge-sensitive signal. during normal operation (not reset), flush# is sampled on every clock edge but is not recognized until the next instruction boundary. if flush# is asserted synchronously, it can be asserted for a minimum of one clock. if flush# is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. flush# is also sampled during the falling transition of reset. if reset and flush# are driven synchronously, flush# is sampled on the clock edge prior to the clock edge on which reset is sampled negated. if reset is driven asynchronously, the minimum setup and hold time for flush#, relative to the negation of reset, is two clocks. 104 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.24 hit# (inquire cycle hit) output summary the processor asserts hit# during an inquire cycle to indicate that the cache line is valid within the processors l1 and/or l2 caches (also known as a cache hit). the cache line can be in the modified, exclusive, or shared state. driven hit# is always drivenexcept in the tri-state test modeand only changes state the clock edge after the clock edge on which eads# is sampled asserted. it is driven in the same state until the next inquire cycle. 4.25 hitm# (inquire cycle hit to modified line) output summary the processor asserts hitm# during an inquire cycle to indicate that the cache line exists in the processors l1 data cache or l2 cache in the modified state. the processor performs a writeback cycle as a result of this cache hit. if an inquire cycle hits a cache line that is currently being written back, the processor asserts hitm# but does not execute another writeback cycle. the system logic must not expect the processor to assert ads# each time hitm# is asserted. driven hitm# is always drivenexcept in the tri-state test mode and, in particular, is driven to represent the result of an inquire cycle the clock edge after the clock edge on which eads# is sampled asserted. if hitm# is negated in response to the inquire address, it remains negated until the next inquire cycle. if hitm# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last brdy# of the writeback is sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 105 4.26 hlda (hold acknowledge) output summary when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. the processor does not assert hlda until the completion of a locked sequence of cycles. while hlda is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor. the following signals are floated when hlda is asserted: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. the processor is designed so that hlda does not glitch. driven hlda is always driven except in the tri-state test mode. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hlda is negated one clock edge after the clock edge on which hold is sampled negated. the assertion of hlda is independent of the sampled state of boff#. the processor floats the bus every clock in which hlda is asserted. 4.27 hold (bus hold request) input summary the system logic can assert hold to gain control of the processors bus. when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. sampled the processor samples hold on every clock edge. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hold is recognized while init and reset are sampled asserted. 10 6 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.28 ignne# (ignore numeric exception) input summary ignne#, in conjunction with the numeric error (ne) bit in cr0, is used by the system logic to control the effect of an unmasked floating-point exception on a previous floating-point instruction during the execution of a floating-point instruction, mmx instruction, 3dnow! instruction, or the wait instruction hereafter referred to as the target instruction. if an unmasked floating-point exception is pending and the target instruction is considered error-sensitive, then the relationship between ne and ignne# is as follows: n if ne = 0, then: ? if ignne# is sampled asserted, the processor ignores the floating-point exception and continues with the execution of the target instruction. ? if ignne# is sampled negated, the processor waits until it samples ignne#, intr, smi#, nmi, or init asserted. if ignne# is sampled asserted while waiting, the processor ignores the floating-point exception and continues with the execution of the target instruction. if intr, smi#, nmi, or init is sampled asserted while waiting, the processor handles its assertion appropriately. n if ne = 1, the processor invokes the int 10h exception handler. if an unmasked floating-point exception is pending and the target instruction is considered error-insensitive, then the processor ignores the floating-point exception and continues with the execution of the target instruction. ferr# is not affected by the state of the ne bit or ignne#. ferr# is always asserted at the instruction boundary of the target instruction that follows the floating-point instruction that caused the unmasked floating-point exception. this signal is provided to allow the system logic to handle exceptions in a manner consistent with ibm-compatible pc/at systems. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 107 sampled the processor samples ignne# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. 4.29 init (initialization) input summary the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers, the cd and nw bits of the cr0 register, and other specific internal resources. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. sampled init is sampled and latched as a rising edge-sensitive signal. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. if init is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 10 8 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.30 intr (maskable interrupt) input summary intr is the systems maskable interrupt input to the processor. when the processor samples and recognizes intr asserted, the processor executes a pair of interrupt acknowledge bus cycles and then jumps to the interrupt service routine specified by the interrupt number that was returned during the interrupt acknowledge sequence. the processor only recognizes intr if the interrupt flag (if) in the eflags register equals 1. sampled the processor samples intr as a level-sensitive input on every clock edge, but the interrupt request is not recognized until the next instruction boundary. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. in order to be recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. 4.31 inv (invalidation request) input summary during an inquire cycle, the state of inv determines whether an addressed cache line that is found in the processors l1 and/or l2 caches transitions to the invalid state or the shared state. if inv is sampled asserted during an inquire cycle, the processor transitions the cache line (if found) to the invalid state, regardless of its previous state. if inv is sampled negated during an inquire cycle, the processor transitions the cache line (if found) to the shared state. in either case, if the cache line is found in the modified state, the processor writes it back to memory before changing its state. sampled inv is sampled on the clock edge on which eads# is sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 109 4.32 ken# (cache enable) input summary if ken# is sampled asserted, it indicates that the address presented by the processor is cacheable. if ken# is sampled asserted and the processor intends to perform a cache-line fill (signified by the assertion of cache#), the processor executes a 32-byte burst read cycle and expects to sample brdy# asserted a total of four times. if ken# is sampled negated during a read cycle, a single-transfer cycle is executed and the processor does not cache the data. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if pcd is asserted during a bus cycle, the processor does not cache any data read during that cycle, regardless of the state of ken# . see pcd (page cache disable) on page 113 for more details. if the processor has sampled the state of ken# during a cycle, and that cycle is aborted due to the sampling of boff# asserted, the system logic must ensure that ken# is sampled in the same state when the processor restarts the aborted cycle. sampled ken# is sampled on the clock edge on which the first brdy# or na# of a read cycle is sampled asserted. if the read cycle is a burst, ken# is ignored during the last three assertions of brdy#. ken# is sampled during read cycles only when cache# is asserted. 110 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.33 lock# (bus lock) output summary the processor asserts lock# during a sequence of bus cycles to ensure that the cycles are completed without allowing other bus masters to intervene. locked operations consist of two to five bus cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors caches are flushed and invalidated from the caches prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor is designed so that lock# does not glitch. driven and floated during a locked cycle, lock# is asserted off the same clock edge on which ads# is asserted and remains asserted until the last brdy# of the last bus cycle is sampled asserted. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. lock# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. when lock# is floated due to boff# sampled asserted, the system logic is responsible for preserving the lock condition while lock# is in the high-impedance state. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 111 4.34 m/io# (memory or i/o) output summary the processor drives m/io# during a bus cycle to indicate whether it is addressing the memory or i/o space. if m/io# = 1, the processor is addressing memory or a memory-mapped i/o port as the result of an instruction fetch or an instruction that loads or stores data. if m/io# = 0, the processor is addressing an i/o port during the execution of an i/o instruction. in addition, m/io# is used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 on page 126 for more details. driven and floated m/io# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. m/io# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. m/io# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. 112 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.35 na# (next address) input summary system logic asserts na# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ads#, along with address and status signals, can be asserted as early as one clock edge after na# is sampled asserted if the processor is prepared to start a new cycle. because the processor allows a maximum of two cycles to be in progress at a time, the assertion of na# is sampled while two cycles are in progress but ads# is not asserted until the completion of the first cycle. sampled na# is sampled every clock edge during bus cycles, starting one clock edge after the clock edge that negates ads#, until the last expected brdy# of the last executed cycle is sampled asserted (with the exception of the clock edge after the clock edge that negates the ads# for a second pending cycle). because the processor latches na# when sampled, the system logic only needs to assert na# for one clock. 4.36 nmi (non-maskable interrupt) input summary when nmi is sampled asserted, the processor jumps to the interrupt service routine defined by interrupt number 02h. unlike the intr signal, software cannot mask the effect of nmi if it is sampled asserted by the processor. however, nmi is temporarily masked upon entering system management mode (smm). in addition, an interrupt acknowledge cycle is not executed because the interrupt number is predefined. if nmi is sampled asserted while the processor is executing the interrupt service routine for a previous nmi, the subsequent nmi remains pending until the completion of the execution of the iret instruction at the end of the interrupt service routine. sampled nmi is sampled and latched as a rising edge-sensitive signal. during normal operation, nmi is sampled on every clock edge but is not recognized until the next instruction boundary. if it is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 113 4.37 pcd (page cache disable) output summary the processor drives pcd to indicate the operating systems specification of cacheability for the page being addressed. system logic can use pcd to control external caching. if pcd is asserted, the addressed page is not cached. if pcd is negated, the cacheability of the addressed page depends upon the state of cache# and ken#. the state of pcd depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pcd output = cd bit in cr0 n in protected and virtual-8086 modes while caching is enabled (cd bit in cr0 set to 0) and paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pcd output = pcd bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pcd output = pcd bit in page directory entry ? for accesses to 4-kbyte pages: pcd output = pcd bit in page table entry driven and floated pcd is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pcd is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. 114 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.38 pchk# (parity check) output summary the processor asserts pchk# during read cycles if it detects an even parity error on one or more valid bytes of d[63:0] during a read cycle. (even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) the processor checks data parity for the data bytes that are valid, as defined by be[7:0]#, the byte enables. pchk# is always driven but is only asserted for memory and i/o read bus cycles and the second cycle of an interrupt acknowledge sequence. pchk# is not driven during any type of write cycles or special bus cycles. the processor does not take an internal exception as the result of detecting a data parity error, and system logic must respond appropriately to the assertion of this signal. the processor is designed so that pchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven pchk# is always driven except in the tri-state test mode. for each brdy# returned to the processor during a read cycle with a parity error detected on the data bus, pchk# is asserted for one clock, one clock edge after brdy# is sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 115 4.39 pwt (page writethrough) output summary the processor drives pwt to indicate the operating systems specification of the writeback state or writethrough state for the page being addressed. pwt, together with wb/wt#, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. see wb/wt# (writeback or writethrough) on page 123 for more details. the state of pwt depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pwt output = 0 (writeback state) n in protected and virtual-8086 modes while paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pwt output = pwt bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pwt output = pwt bit in page directory entry ? for accesses to 4-kbyte pages: pwt output = pwt bit in page table entry driven and floated pwt is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pwt is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. 116 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 4.40 reset (reset) input summary when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the mmx state, the 3dnow! state, and all registers, and then the processor jumps to address ffff_fff0h to start instruction execution. the flush# signal is sampled during the falling transition of reset to invoke the tri-state test mode. sampled reset is sampled as a level-sensitive input on every clock edge. system logic can drive the signal either synchronously or asynchronously. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification before it is negated. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 4.41 rsvd (reserved) summary reserved signals are a special class of pins that can be treated in one of the following ways: n as no-connect (nc) pins, in which case these pins are left unconnected n as pins connected to the system logic as defined by the industry-standard super7 and socket 7 interface n any combination of nc and socket 7 pins in any case, if the rsvd pins are treated accordingly, the normal operation of the AMD-K6-III processor is not adversely affected in any manner. see pin designations on page 295 for a list of the locations of the rsvd pins. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 117 4.42 scyc (split cycle) output summary the processor asserts scyc during misaligned, locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. for purposes of bus cycles, the term aligned means: n any 1-byte transfers n 2-byte and 4-byte transfers that lie within 4-byte address boundaries n 8-byte transfers that lie within 8-byte address boundaries driven and floated scyc is asserted off the same clock edge as ads#, and negated off the clock edge on which na# or the last expected brdy# of the entire locked sequence is sampled asserted. scyc is only valid during locked memory cycles. scyc is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. 4.43 smi# (system management interrupt) input, internal pullup summary the assertion of smi# causes the processor to enter system management mode (smm). upon recognizing smi#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the interrupt by asserting smiact# after sampling ewbe# asserted (if ewbe# is masked off, then smiact# is not affected by ewbe#) 4. saves the internal processor state in smm memory 5. disables interrupts by clearing the interrupt flag (if) in eflags and disables nmi interrupts 6. jumps to the entry point of the smm service routine at the smm base physical address which defaults to 0003_8000h in smm memory 118 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 see system management mode (smm) on page 213 for more details regarding smm. sampled smi# is sampled and latched as a falling edge-sensitive signal. smi# is sampled on every clock edge but is not recognized until the next instruction boundary. if smi# is to be recognized on the instruction boundary associated with a brdy#, it must be sampled asserted a minimum of three clock edges before the brdy# is sampled asserted. if it is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks followed by an assertion of a minimum of two clocks. a second assertion of smi# while in smm is latched but is not recognized until the smm service routine is exited. 4.44 smiact# (system management interrupt active) output summary the processor acknowledges the assertion of smi# with the assertion of smiact# to indicate that the processor has entered system management mode (smm). the system logic can use smiact# to enable smm memory. see smi# (system management interrupt) on page 117 for more details. see system management mode (smm) on page 213 for more details regarding smm. driven the processor asserts smiact# after the last brdy# of the last pending bus cycle is sampled asserted (including all pending write cycles) and after ewbe# is sampled asserted (if ewbe# is masked off, then smiact# is not affected by ewbe#). smiact# remains asserted until after the last brdy# of the last pending bus cycle associated with exiting smm is sampled asserted. smiact# remains asserted during any flush, internal snoop, or writeback cycle due to an inquire cycle. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 119 4.45 stpclk# (stop clock) input, internal pullup summary the assertion of stpclk# causes the processor to enter the stop grant state, during which the processors internal clock is stopped. from the stop grant state, the processor can subsequently transition to the stop clock state, in which the bus clock clk is stopped. upon recognizing stpclk#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the stpclk# assertion by executing a stop grant special bus cycle (see table 23 on page 126) 4. stops its internal clock after brdy# of the stop grant special bus cycle is sampled asserted and after ewbe# is sampled asserted (if ewbe# is masked off, then entry into the stop grant state is not affected by ewbe#) 5. enters the stop clock state if the system logic stops the bus clock clk (optional) see clock control on page 249 for more details regarding clock control. sampled stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle. 4.46 tck (test clock) input, internal pullup summary tck is the clock for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 225 for details regarding the operation of the tap controller. 120 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 sampled the processor always samples tck, except while trst# is asserted. 4.47 tdi (test data input) input, internal pullup summary tdi is the serial test data and instruction input for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 225 for details regarding the operation of the tap controller. sampled the processor samples tdi on every rising tck edge but only while in the shift-ir and shift-dr states. 4.48 tdo (test data output) output summary tdo is the serial test data and instruction output for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 225 for details regarding the operation of the tap controller. driven and floated the processor drives tdo on every falling tck edge but only while in the shift-ir and shift-dr states. tdo is floated at all other times. 4.49 tms (test mode select) input, internal pullup summary tms specifies the test function and sequence of state changes for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 225 for details regarding the operation of the tap controller. sampled the processor samples tms on every rising tck edge. if tms is sampled high for five or more consecutive clocks, the tap controller enters its test-logic-reset state, regardless of the controller state. this action is the same as that achieved by asserting trst#. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 121 4.50 trst# (test reset) input, internal pullup summary the assertion of trst# initializes the test access port (tap) by resetting its state machine to the test-logic-reset state. see boundary-scan test access port (tap) on page 225 for details regarding the operation of the tap controller. sampled trst# is a completely asynchronous input that does not require a minimum setup and hold time relative to tck. see table 62 on page 280 for the minimum pulse width requirement. 4.51 vcc2det (v cc2 detect) output summary vcc2det is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the v cc2 and v cc3 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low, system logic should sample vcc2h/l# to identify core voltage requirements. driven vcc2det always equals 0 and is never floatedeven during the tri-state test mode. 4.52 vcc2h/l# (v cc2 high/low) output summary vcc2h/l# is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the v cc2 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low to identify dual-voltage processor requirements, system logic should sample vcc2h/l# to identify the core voltage requirements for 2.9v and 3.2v products (high) or 2.2v and 2.4v products (low). driven vcc2h/l# always equals 0 and is never floated for 2.2v and 2.4v productseven during the tri-state test mode. to ensure proper operation for 2.9v and 3.2v products, system logic that 122 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 samples vcc2h/l# should design a weak pullup resistor for this signal. 4.53 w/r# (write/read) output summary the processor drives w/r# to indicate whether it is performing a write or a read cycle on the bus. in addition, w/r# is used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 on page 126 for more details. driven and floated w/r# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. w/r# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. w/r# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. table 17. output pin float conditions name floated at: note vcc2det always driven * vcc2h/l# always driven * note: * all outputs except vcc2det, vcc2h/l#, and tdo float during the tri-state test mode. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 123 4.54 wb/wt# (writeback or writethrough) input summary wb/wt#, together with pwt, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. if wb/wt# = 0 or pwt = 1 during a cacheable read miss or write hit to a shared cache line, the accessed line is cached in the shared state. this is referred to as the writethrough state because all write cycles to this cache line are driven externally on the bus. if wb/wt# = 1 and pwt = 0 during a cacheable read miss or a write hit to a shared cache line, the accessed line is cached in the exclusive state. subsequent write hits to the same line cause its state to transition from exclusive to modified. this is referred to as the writeback state because the l1 data cache and the l2 cache can contain modified cache lines that are subject to be written backreferred to as a writeback cycleas the result of an inquire cycle, an internal snoop, a flush operation, or the wbinvd instruction. sampled wb/wt# is sampled on the clock edge that the first brdy# or na# of a bus cycle is sampled asserted. if the cycle is a burst read, wb/wt# is ignored during the last three assertions of brdy#. wb/wt# is sampled during memory read and non-writeback write cycles and is ignored during all other types of cycles. 124 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 18. input pin types name type note name type note a20m# asynchronous 1 ignne# asynchronous 1 ahold synchronous init asynchronous 2 bf[2:0] synchronous 4 intr asynchronous 1 boff# synchronous inv synchronous brdy# synchronous ken# synchronous brdyc# synchronous na# synchronous clk clock nmi asynchronous 2 eads# synchronous reset asynchronous 5, 6 ewbe# synchronous 7 smi# asynchronous 2 flush# asynchronous 2, 3 stpclk# asynchronous 1 hold synchronous wb/wt# synchronous notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 3. flush # is also sampled during the falling transition of reset and can be asserted synchronously or asynchronously. to be sam- pled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which reset is sampled negated. if asserted asynchronously, flush# must meet a minimum setup and hold time of two clocks relative to the negation of reset. 4. bf[2:0] are sampled during the falling transition of reset. they must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of r eset. 5. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification before it is negated. 6. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 7. on the amd-k6- iii processor, if efer[3] is set to 1, then ewbe# is ignored by the processor. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 4 signal descriptions 125 table 19. output pin float conditions name floated at: (note 1) note name floated at: (note 1) note a[4:3] hlda, ahold, boff# 2, 3 hlda always driven ads# hlda, boff# 2 lock# hlda, boff# 2 adsc# hlda, boff# 2 m/io# hlda, boff# 2 apchk# always driven pcd hlda, boff# 2 be[7:0]# hlda, boff# 2 pchk# always driven breq always driven pwt hlda, boff# 2 cache# hlda, boff# 2 scyc hlda, boff# 2 d/c# hlda, boff# 2 smiact# always driven ferr# always driven vcc2det always driven hit# always driven vcc2h/l# always driven hitm# always driven w/r# hlda, boff# 2 notes: 1. all outputs except vcc2det, vcc2h/l#, and tdo float during the tri-state test mode. 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. table 20. input/output pin float conditions name floated at: (note 1) note a[31:5] hlda, ahold, boff# 2,3 ap hlda, ahold, boff# 2,3 d[63:0] hlda, boff# 2 dp[7:0] hlda, boff# 2 notes: 1. all outputs except vcc2det and tdo float during the tri-state test mode. 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. table 21. test pins name type note tck clock tdi input sampled on the rising edge of tck tdo output driven on the falling edge of tck tms input sampled on the rising edge of tck trst# input asynchronous (independent of tck) 126 signal descriptions chapter 4 amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 22. bus cycle definition bus cycle initiated generated by the processor generated by the system m/io# d/c# w/r# cache# ken# code read, l1 instruction cache and l2 cache line fill 1 0 0 0 0 code read, noncacheable 1 0 0 1 x code read, noncacheable 1 0 0 x 1 encoding for special cycle 0 0 1 1 x interrupt acknowledge 0 0 0 1 x i/o read 0 1 0 1 x i/o write 0 1 1 1 x memory read, l1 data cache and l2 cache line fill 1 1 0 0 0 memory read, noncacheable 1 1 0 1 x memory read, noncacheable 1 1 0 x 1 memory write, l1 data cache or l2 cache writeback 1 1 1 0 x memory write, noncacheable 1 1 1 1 x note: x means dont care table 23. special cycles special cycle a4 be7# be6# be5# be4# be3# be2# be1# be0# m/io# d/c# w/r# cache# ken# stop grant 1111110110011x flush acknowledge (flush# sampled asserted) 0111011110011x writeback (wbinvd instruction) 0111101110011x halt 0111110110011x flush (invd, wbinvd instruction) 0111111010011x shutdown 0111111100011x note: x means dont care 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 127 5 bus cycles the following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. a representative set of bus cycles is illustrated. 5.1 timing diagrams the timing diagrams illustrate the signals on the external local bus as a function of time, as measured by the bus clock (clk). throughout this chapter, the term clock refers to a single bus-clock cycle. a clock extends from one rising clk edge to the next rising clk edge. the processor samples and drives most signals relative to the rising edge of clk. the exceptions to this rule include the following: n bf[2:0]sampled on the falling edge of reset n flush#sampled on the falling edge of reset, also sampled on the rising edge of clk n all inputs and outputs are sampled relative to tck in boundary-scan test mode. inputs are sampled on the rising edge of tck, outputs are driven off of the falling edge of tck. for each signal in the timing diagrams, the high level represents 1, the low level represents 0, and the middle level represents the floating (high-impedance) state. when both the high and low levels are shown, the meaning depends on the signal. a single signal indicates dont care. in the case of bus activity, if both high and low levels are shown, it indicates the processor, alternate master, or system logic is driving a value, but this value may or may not be valid. (for example, the value on the address bus is valid only during the assertion of ads#, but addresses are also driven on the bus at other times.) figure 54 defines the different waveform representations. 128 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 54. waveform definitions for all active-high signals, the term asserted means the signal is in the high-voltage state and the term negated means the signal is in the low-voltage state. for all active-low signals, the term asserted means the signal is in the low-voltage state and the term negated means the signal is in the high-voltage state. waveform dont care or bus is driven description signal or bus is changing from low to high signal or bus is changing from high to low bus is changing bus is changing from valid to invalid signal or bus is floating denotes multiple clock periods 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 129 5.2 bus state machine diagram figure 55. bus state machine diagram last brdy# last brdy# bus transition? no yes yes yes yes no no no no pending request? na# sampled asserted? na# sampled asserted? asserted? asserted? addr data pipe-a pipe-d idle trans bus state branch condition idle data pipeline address transition address pipeline data note: the processor transitions to the idle state on the clock edge on which boff# or reset is sampled asserted. data-na# requested data-na# last brdy# yes no asserted? pending request? no yes no yes yes na# sampled asserted? yes no 130 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 idle the processor does not drive the system bus in the idle state and remains in this state until a new bus cycle is requested. the processor enters this state off the clock edge on which the last brdy# of a cycle is sampled asserted during the following conditions: n the processor is in the data state n the processor is in the data-na# requested state and no internal pending cycle is requested in addition, the processor is forced into this state when the system logic asserts reset or boff#. the transition to this state occurs on the clock edge on which reset or boff# is sampled asserted. address in this state, the processor drives ads# to indicate the beginning of a new bus cycle by validating the address and control signals. the processor remains in this state for one clock and unconditionally enters the data state on the next clock edge. data in the data state, the processor drives the data bus during a write cycle or expects data to be returned during a read cycle. the processor remains in this state until either na# or the last brdy# is sampled asserted. if the last brdy# is sampled asserted or both the last brdy# and na# are sampled asserted on the same clock edge, the processor enters the idle state. if na# is sampled asserted first, the processor enters the data-na# requested state. data-na# requested if the processor samples na# asserted while in the data state and the current bus cycle is not completed (the last brdy# is not sampled asserted), it enters the data-na# requested state. the processor remains in this state until either the last brdy# is sampled asserted or an internal pending cycle is requested. if the last brdy# is sampled asserted before the processor drives a new bus cycle, the processor enters the idle state (no internal pending cycle is requested) or the address state (processor has a internal pending cycle). pipeline address in this state, the processor drives ads# to indicate the beginning of a new bus cycle by validating the address and control signals. in this state, the processor is still waiting for the current bus cycle to be completed (until the last brdy# is 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 131 sampled asserted). if the last brdy# is not sampled asserted, the processor enters the pipeline data state. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. a bus transition is required when the data bus direction changes between bus cycles, such as a memory write cycle followed by a memory read cycle. if a bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state. the processor does not transition to the data-na# requested state from the pipeline address state because the processor does not begin sampling na# until it has exited the pipeline address state. pipeline data two bus cycles are concurrently executing in this state. the processor cannot issue any additional bus cycles until the current bus cycle is completed. the processor drives the data bus during write cycles or expects data to be returned during read cycles for the current bus cycle until the last brdy# of the current bus cycle is sampled asserted. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. if the bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state (na# was not sampled asserted) or the data-na# requested state (na# was sampled asserted). transition the processor enters this state for one clock during data bus transitions and enters the data state on the next clock edge if na# is not sampled asserted. the sole purpose of this state is to avoid bus contention caused by bus transitions during pipeline operation. 132 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 5.3 memory reads and writes the AMD-K6-III processor performs single or burst memory bus cycles. the single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. a burst cycle consists of four back-to-back 8-byte (64-bit) transfers on the data bus. single-transfer memory read and write figure 56 shows a single-transfer read from memory, followed by two single-transfer writes to memory. for the memory read cycle, the processor asserts ads# for one clock to validate the bus cycle and also drives a[31:3], be[7:0]#, d/c#, w/r#, and m/io# to the bus. the processor then waits for the system logic to return the data on d[63:0] (with dp[7:0] for parity checking) and assert brdy#. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads# . see brdy# (burst ready) on page 94. during the read cycle, the processor drives pcd, pwt, and cache# to indicate its caching and cache-coherency intent for the access. the system logic returns ken# and wb/wt# to either confirm or change this intent. if the processor asserts pcd and negates cache#, the accesses are noncacheable, even though the system logic asserts ken# during the brdy# to indicate its support for cacheability. the processor (which drives cache#) and the system logic (which drives ken#) must agree in order for an access to be cacheable. the processor can drive another cycle (in this example, a write cycle) by asserting ads# off the next clock edge after brdy# is sampled asserted. therefore, an idle clock is guaranteed between any two bus cycles. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. to minimize processor idle times, the system logic stores the address and data in write buffers, returns brdy#, and performs the store to memory later. if the processor samples ewbe# negated during a write cycle, it suspends certain activities until ewbe# is sampled asserted. see ewbe# (external write buffer empty) on page 101. in figure 56, the second write cycle occurs during the execution of a serializing instruction. the processor delays the following cycle until ewbe# is sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 133 figure 56. non-pipelined single-transfer memory read/write and write delayed by ewbe# read cycle write cycle (next cycle delayed by ewbe#) write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# breq d[63:0] dp[7:0] cache# ewbe# ken# brdy# wb/wt# addr data idle addr addr data idle data data data idle idle idle idle idle addr 134 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 misaligned single-transfer memory read and write figure 57 shows a misaligned (split) memory read followed by a misaligned memory write. any cycle that is not aligned as defined in scyc (split cycle) on page 117 is considered misaligned. when the processor encounters a misaligned access, it determines the appropriate pair of bus cycleseach with its own ads# and brdy# required to complete the access. the AMD-K6-III processor performs misaligned memory reads and memory writes using least-significant bytes (lsbs) first followed by most-significant bytes (msbs). table 24 shows the order. in the first memory read cycle in figure 57, the processor reads the least-significant bytes. immediately after the processor samples brdy# asserted, it drives the second bus cycle to read the most-significant bytes to complete the misaligned transfer. similarly, the misaligned memory write cycle in figure 57 on page 135 transfers the lsbs to the memory bus first. in the next cycle, after the processor samples brdy# asserted, the msbs are written to the memory bus. table 24. bus-cycle order during misaligned transfers type of access first cycle second cycle memory read lsbs msbs memory write lsbs msbs 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 135 figure 57. misaligned single-transfer memory read and write lsb msb lsb msb memory read (misaligned) memory write (misaligned) clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data idle data addr data data idl e data 136 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 burst reads and pipelined burst reads figure 58 shows normal burst read cycles and a pipelined burst read cycle. the AMD-K6-III processor drives cache# and ads# together to specify that the current bus cycle is a burst cycle. if the processor samples ken# asserted with the first brdy#, it performs burst transfers. during the burst transfers, the system logic must ignore be[7:0]# and must return all eight bytes beginning at the starting address the processor asserts on a[31:3]. depending on the starting address, the system logic must determine the successive quadword addresses (a[4:3]) for each transfer in a burst, as shown in table 25. the processor expects the second, third, and fourth quadwords to occur in the sequences shown in table 25. in figure 58, the processor drives cache# throughout all burst read cycles. in the first burst read cycle, the processor drives ads# and cache#, then samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the processor samples ken# asserted on the clock edge on which the first brdy# is sampled asserted, executes a 32-byte burst read cycle, and expects a total of four brdy# signals. an ideal no-wait state access is shown in figure 58, whereas most system logic solutions add wait states between the transfers. the second burst read cycle illustrates a similar sequence, but the processor samples na# asserted on the same clock edge that the first brdy# is sampled asserted. na# assertion indicates the system logic is requesting the processor to output the next address early (also known as a pipeline transfer request). without waiting for the current cycle to complete, the processor drives ads# and related signals for the next burst cycle. pipelining can reduce processor cycle-to-cycle idle times. table 25. a[4:3] address-generation sequence during bursts address driven by processor on a[4:3] a[4:3] addresses of subsequent quadwords* generated by system logic quadword 1 quadword 2 quadword 3 quadword 4 00b 01b 10b 11b 01b 00b 11b 10b 10b 11b 00b 01b 11b 10b 01b 00b note: * quadword = 8 bytes 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 137 figure 58. burst reads and pipelined burst reads -na -addr data1 data2 data3 burst read pipelined burst read addr1 addr2 addr3 burst read clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# na# d[63:0] cache# ken# brdy# addr data idle data data data addr data data data pipe data data data data i dle 138 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 burst writeback figure 59 shows a burst read followed by a writeback transaction. the AMD-K6-III processor initiates writebacks under the following conditions: n replacement if a cache-line fill is initiated for a cache line currently filled with valid entries, the processor selects a line for replacement based on a least-recently-used (lru) algorithm for the l1 instruction cache and the l2 cache, and a least-recently-allocated (lra) algorithm for the l1 data cache. before a replacement is made to a l1 data cache or l2 cache line that is in the modified state, the modified line is scheduled to be written back to memory. n internal snoop the processor snoops its l1 instruction cache during read or write misses to its l1 data cache, and it snoops its l1 data cache during read misses to its l1 instruction cache. this snooping is performed to determine whether the same address is stored in both caches, a situation that is taken to imply the occurrence of self-modifying code. if an internal snoop hits a l1 data cache line in the modified state, the line is written back to memory before being invalidated. n wbinvd instruction when the processor executes a wbinvd instruction, it writes back all modified lines in the l1 data cache and l2 cache, and then invalidates all lines in all caches. n cache flush when the processor samples flush# asserted, it executes a flush acknowledge special cycle and writes back all modified lines in the l1 data cache and l2 cache, and then invalidates all lines in all caches. the processor drives writeback cycles during inquire or cache flush cycles. the writeback shown in figure 59 is caused by a cache-line replacement. the processor completes the burst read cycle that fills the cache line. immediately following the burst read cycle is the burst writeback cycle that represents the modified line to be written back to memory. d[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each of the four brdy# signals of the burst cycle are sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 139 figure 59. burst writeback due to cache-line replacement burst read burst writeback from l1 cache clk a[31:3] be[7:0]# ads# cache# m/io# d/c# w/r# d[63:0] ken# brdy# wb/wt# addr data idle data data data addr data idle data data data 14 0 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 5.4 i/o read and write basic i/o read and write the processor accesses i/o when it executes an i/o instruction (for example, in or out). figure 60 shows an i/o read followed by an i/o write. the processor drives m/io# low and d/c# high during i/o cycles. in this example, the first cycle shows a single wait state i/o read cycle. it follows the same sequence as a single-transfer memory read cycle. the processor drives ads# to initiate the bus cycle, then it samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the system logic must return brdy# to complete the cycle. when the processor samples brdy# asserted, it can assert ads# for the next cycle off the next clock edge. (in this example, an i/o write cycle.) the i/o write cycle is similar to a memory write cycle, but the processor drives m/io# low during an i/o write cycle. the processor asserts ads# to initiate the bus cycle. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. the system logic must assert brdy# when the data is properly stored to the i/o destination. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. in this example, two wait states are inserted while the processor waits for brdy# to be asserted. figure 60. basic i/o read and write i/o read cycle i/o write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data data idle 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 141 misaligned i/o read and write table 26 shows the misaligned i/o read and write cycle order executed by the AMD-K6-III processor. in figure 61, the least-significant bytes (lsbs) are transferred first. immediately after the processor samples brdy# asserted, it drives the second bus cycle to transfer the most-significant bytes (msbs) to complete the misaligned bus cycle. figure 61. misaligned i/o transfer table 26. bus-cycle order during misaligned i/o transfers type of access first cycle second cycle i/o read lsbs msbs i/o write lsbs msbs lsb msb lsb msb misaligned i/o read misaligned i/o write clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data data idle addr data data data idle scyc 142 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 5.5 inquire and bus arbitration cycles the AMD-K6-III processor provides built-in level-one (l1) data and instruction caches, and a unified level-two (l2) cache. each l1 cache is 32 kbytes and two-way set-associative. the l2 cache is 256 kbytes and four-way set-associative. the system logic or other bus master devices can initiate an inquire cycle to maintain cache/memory coherency. in response to the inquire cycle, the processor compares the inquire address with its cache tag addresses in all caches, and, if necessary, updates the mesi state of the cache line and performs writebacks to memory. an inquire cycle can be initiated by asserting ahold, boff#, or hold. ahold is exclusively used to support inquire cycles. during ahold-initiated inquire cycles, the processor only floats the address bus. boff# provides the fastest access to the bus because it aborts any processor cycle that is in-progress, whereas ahold and hold both permit an in-progress bus cycle to complete. during hold-initiated and boff#-initiated inquire cycles, the processor floats all of its bus-driving signals. hold and hold acknowledge cycle the system logic or another bus device can assert hold to initiate an inquire cycle or to gain full control of the bus. when the AMD-K6-III processor samples hold asserted, it completes any in-progress bus cycle and asserts hlda to acknowledge release of the bus. the processor floats the following signals off the same clock edge that hlda is asserted: figure 62 shows a basic hold/hlda operation. in this example, the processor samples hold asserted during the memory read cycle. it continues the current memory read cycle until brdy# is sampled asserted. the processor drives hlda and floats its outputs one clock edge after the last brdy# of the cycle is sampled asserted. the system logic can assert hold for as long as it needs to utilize the bus. the processor samples n a[31:3] n dp[7:0] n ads# n lock# n ap# n m/io# n be[7:0]# n pcd n cache# n pwt n d[63:0] n scyc n d/c# n w/r# 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 143 hold on every clock edge but does not assert hlda until any in-progress cycle or sequence of locked cycles is completed. when the processor samples hold negated during a hold acknowledge cycle, it negates hlda off the next clock edge. the processor regains control of the bus and can assert ads# off the same clock edge on which hlda is negated. figure 62. basic hold/hlda operation clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] hold hlda brdy# 144 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 hold-initiated inquire hit to shared or exclusive line figure 63 shows a hold-initiated inquire cycle. in this example, the processor samples hold asserted during the burst memory read cycle. the processor completes the current cycle (until the last expected brdy# is sampled asserted), asserts hlda and floats its outputs as described on page 142. the system logic drives an inquire cycle within the hold acknowledge cycle. it asserts eads#, which validates the inquire address on a[31:5]. if eads# is sampled asserted before hold is sampled negated, the processor recognizes it as a valid inquire cycle. in figure 63, the processor asserts hit# and negates hitm# on the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hit a shared or exclusive cache line. ( s hared and exclusive cache lines have not been modified and do not need to be written back.) during an inquire cycle, the processor samples inv to determine whether the addressed cache line found in the processors caches transitions to the invalid state or the shared state. in this example, the processor samples inv asserted with eads#, which invalidates the cache line. the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor continues driving hit# in the same state until the next inquire cycle. hitm# is not asserted unless hit# is asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 145 figure 63. hold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# hold hlda eads# inv 146 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 hold-initiated inquire hit to modified line figure 64 shows the same sequence as figure 63, but in figure 64 the inquire cycle hits a modified line and the processor asserts both hit# and hitm#. in this example, the processor performs a writeback cycle immediately after the inquire cycle. it updates the modified cache line to external memory (normally, external cache or dram). the processor uses the address (a[31:5]) that was latched during the inquire cycle to perform the writeback cycle. the processor asserts hitm# throughout the writeback cycle and negates hitm# one clock edge after the last expected brdy# of the writeback is sampled asserted. when the processor samples eads# during the inquire cycle, it also samples inv to determine the cache line mesi state after the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state. the cache line invalidation operation is not visible on the bus. if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in figure 64 the processor samples inv asserted during the inquire cycle. in a hold-initiated inquire cycle, the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor drives hit# and hitm# on the clock edge after the clock edge on which eads# is sampled asserted. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 147 figure 64. hold-initiated inquire hit to modified line burst memory read inquire writeback cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# eads# hit# hitm# d[63:0] ken# brdy# hold hlda inv 148 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 ahold-initiated inquire miss ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this functionality allows a bus cycle in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. in figure 65, the processor samples ahold asserted during the memory burst read cycle, and it floats the address bus off the same clock edge on which it samples ahold asserted. while the processor still controls the bus, it completes the current cycle until the last expected brdy# is sampled asserted. the system logic drives eads# with an inquire address on a[31:5] during an inquire cycle. the processor samples eads# asserted and compares the inquire address to its tag address in the l1 instruction and data caches, and in the l2 cache. in figure 65, the inquire address misses the tag address in the processor (both hit# and hitm# are negated). therefore, the processor proceeds to the next cycle when it samples ahold negated. (the processor can drive a new cycle by asserting ads# off the same clock edge that it samples ahold negated.) for an ahold-initiated inquire cycle to be recognized, the processor must sample ahold asserted for at least two consecutive clocks before it samples eads# asserted. if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the system logic must respond appropriately to the assertion of this signal. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 149 figure 65. ahold-initiated inquire miss read inquire clk a[31:3] be[7:0]# ap apchk# ads# hit# hitm# d[63:0] ken# brdy# ahold eads# inv 150 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 ahold-initiated inquire hit to shared or exclusive line in figure 66, the processor asserts hit# and negates hitm# off the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hits either a shared or exclusive line. (hit# is driven in the same state until the next inquire cycle.) the processor samples inv asserted during the inquire cycle and transitions the line to the invalid state regardless of its previous state. during an ahold-initiated inquire cycle, the processor samples ahold on every clock edge until it is negated. in figure 66, the processor asserts ads# off the same clock on which ahold is sampled negated. if the inquire cycle hits a modified line, the processor performs a writeback cycle before it drives a new bus cycle. the next section describes the ahold-initiated inquire cycle that hits a modified line. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 151 figure 66. ahold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold inv eads# 152 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 ahold-initiated inquire hit to modified line figure 67 shows an ahold-initiated inquire cycle that hits a modified line. during the inquire cycle in this example, the processor asserts both hit# and hitm# on the clock edge after the clock edge that it samples eads# asserted. this condition indicates that the cache line exists in the processors l1 data cache or l2 cache in the modified state. if the inquire cycle hits a modified line, the processor performs a writeback cycle immediately after the inquire cycle to update the modified cache line to shared memory (normally external cache or dram). in figure 67, the system logic holds ahold asserted throughout the inquire cycle and the processor writeback cycle. in this case, the processor is not driving the address bus during the writeback cycle because ahold is sampled asserted. the system logic writes the data to memory by using its latched copy of the inquire cycle address. if the processor samples ahold negated before it performs the writeback cycle, it drives the writeback cycle by using the address (a[31:5]) that it latched during the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state (the cache invalidation operation is not visible on the bus). if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in either case, if the line is found in the modified state, the processor writes it back to memory before changing its state. figure 67 shows that the processor samples inv asserted during the inquire cycle and invalidates the cache line after the inquire cycle. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 153 figure 67. ahold-initiated inquire hit to modified line burst memory read inquire writeback clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold eads# inv 154 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 ahold restriction when the system logic drives an ahold-initiated inquire cycle, it must assert ahold for at least two clocks before it asserts eads#. this requirement guarantees the processor recognizes and responds to the inquire cycle properly. the processors 32 address bus drivers turn on almost immediately after ahold is sampled negated. if the processor switches the data bus (d[63:0] and dp[7:0]) during a write cycle off the same clock edge that switches the address bus (a[31:3] and ap), the processor switches 102 drivers simultaneously, which can lead to ground-bounce spikes. therefore, before negating ahold the following restrictions must be observed by the system logic: n when the system logic negates ahold during a write cycle, it must ensure that ahold is not sampled negated on the clock edge on which brdy# is sampled asserted (see figure 68). n when the system logic negates ahold during a writeback cycle, it must ensure that ahold is not sampled negated on the clock edge on which ads# is negated (see figure 68). n when a write cycle is pipelined into a read cycle, ahold must not be sampled negated on the clock edge after the clock edge on which the last brdy# of the read cycle is sampled asserted to avoid the processor simultaneously driving the data bus (for the pending write cycle) and the address bus off this same clock edge. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 155 figure 68. ahold restriction the system must ensure that ahold is not sampled negated on the clock edge that ads # is negated. legal ahold negation during write cycle illegal ahold negation during write cycle clk ads# w/r# hitm# eads# d[63:0] brdy# ahold the system must ensure that ahold is not sampled negated on the clock edge on which brdy # is sample d asserted . 156 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 bus backoff (boff#) boff# provides the fastest response among bus-hold inputs. either the system logic or another bus master can assert boff# to gain control of the bus immediately. boff# is also used to resolve potential deadlock problems that arise as a result of inquire cycles. the processor samples boff# on every clock edge. if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state. (see boff# (backoff) on page 93.) figure 69 shows a read cycle that is aborted when the processor samples boff# asserted even though brdy# is sampled asserted on the same clock edge. the read cycle is restarted after boff# is sampled negated (ken# must be in the same state during the restarted cycle as its state during the aborted cycle). during a boff#-initiated inquire cycle that hits a shared or exclusive line, the processor samples boff# negated and restarts any bus cycle that was aborted when boff# was asserted. if a boff#-initiated inquire cycle hits a modified line, the processor performs a writeback cycle before it restarts the aborted cycle. if the processor samples boff# asserted on the same clock edge that it asserts ads#, ads# is floated but the system logic may erroneously interpret ads# as asserted. in this case, the system logic must properly interpret the state of ads# when boff# is negated. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 157 figure 69. boff# timing read back off cycle restart read cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# boff# d[63:0] brdy# 158 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 locked cycles the processor asserts lock# during a sequence of bus cycles to ensure the cycles are completed without allowing other bus masters to intervene. locked operations can consist of two to five cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors caches are flushed and invalidated from the caches prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. the processor asserts scyc during misaligned locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. basic locked operation figure 70 shows a pair of read-write bus cycles. it represents a typical read-modify-write locked operation. the processor asserts lock# off the same clock edge that it asserts ads# of the first bus cycle in the locked operation and holds it asserted until the last expected brdy# of the last bus cycle in the locked operation is sampled asserted. (the processor negates lock# off the same clock edge.) 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 159 figure 70. basic locked operation locked read cycle locked write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] brdy# addr data data data idle idle addr data data data idle idle addr scyc 16 0 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 locked operation with boff# intervention figure 71 shows boff# asserted within a locked read-write pair of bus cycles. in this example, the processor asserts lock# with ads# to drive a locked memory read cycle followed by a locked memory write cycle. during the locked memory write cycle in this example, the processor samples boff# asserted. the processor immediately aborts the locked memory write cycle and floats all its bus-driving signals, including lock#. the system logic or another bus master can initiate an inquire cycle or drive a new bus cycle one clock edge after the clock edge on which boff# is sampled asserted. if the system logic drives a boff#-initiated inquire cycle and hits a modified line, the processor performs a writeback cycle before it restarts the locked cycle (the processor asserts lock# during the writeback cycle). in figure 71, the processor immediately restarts the aborted locked write cycle by driving the bus off the clock edge on which boff# is sampled negated. the system logic must ensure the processor results for interrupted and uninterrupted locked cycles are consistent. that is, the system logic must guarantee the memory accessed by the processor is not modified during the time another bus master controls the bus. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 161 figure 71. locked operation with boff# intervention locked read cycle aborted write cycle restart write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# boff# d[63:0] brdy# 162 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 interrupt acknowledge in response to recognizing the systems maskable interrupt (intr), the processor drives an interrupt acknowledge cycle at the next instruction boundary. during an interrupt acknowledge cycle, the processor drives a locked pair of read cycles as shown in figure 72. the first read cycle is not functional, and the second read cycle returns the interrupt number on d[7:0] (00hCffh). table 27 shows the state of the signals during an interrupt acknowledge cycle. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. to ensure it is recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. table 27. interrupt acknowledge operation definition processor outputs first bus cycle second bus cycle d/c# low low m/io# low low w/r# low low be[7:0]# efh feh (low byte enabled) a[31:3] 0000_0000h 0000_0000h d[63:0] (ignored) interrupt number expected from interrupt controller on d[7:0] 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 163 figure 72. interrupt acknowledge operation interrupt acknowledge cycles interrupt number clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# lock# intr d[63:0] ken# brdy# 164 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 5.6 special bus cycles the AMD-K6-III processor drives special bus cycles that include stop grant, flush acknowledge, cache writeback invalidation, halt, cache invalidation, and shutdown cycles. during all special cycles, d/c# = 0, m/io# = 0, and w/r# = 1. be[7:0]# and a[31:3] are driven to differentiate among the special cycles, as shown in table 28. the system logic must return brdy# in response to all processor special cycles. basic special bus cycle figure 73 shows a basic special bus cycle. the processor drives d/c# = 0, m/io# = 0, and w/r# = 1 off the same clock edge that it asserts ads#. in this example, be[7:0]# = fbh and a[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (see table 28). a halt special cycle is generated after the processor executes the hlt instruction. if the processor samples flush# asserted, it writes back any l1 data cache and l2 cache lines that are in the modified state and invalidates all lines in all caches. the processor then drives a flush acknowledge special cycle. if the processor executes a wbinvd instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines. table 28. encodings for special bus cycles be[7:0]# a[4:3]* special bus cycle cause fbh 10b stop grant stpclk# sampled asserted efh 00b flush acknowledge flush# sampled asserted f7h 00b writeback wbinvd instruction fbh 00b halt hlt instruction fdh 00b flush invd,wbinvd instruction feh 00b shutdown triple fault note: * a[31:5] = 0 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 165 figure 73. basic special bus cycle (halt cycle) halt cycle a[4:3] = 00b fbh clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# brdy# 16 6 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 shutdown cycle in figure 74, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle follows in the second half. the processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (int 8), which amounts to a triple fault. when the processor encounters a triple fault, it stops its activity on the bus and generates the shutdown special bus cycle (be[7:0]# = feh). the system logic must assert nmi, init, reset, or smi# to get the processor out of the shutdown state. figure 74. shutdown cycle shutdown occurs (triple fault) shutdown special cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] ken# brdy# a[4:3] = 00b feh 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 167 stop grant and stop clock states figure 75 and figure 76 show the processor transition from normal execution to the stop grant state, then to the stop clock state, back to the stop grant state, and finally back to normal execution. the series of transitions begins when the processor samples stpclk# asserted. on recognizing a stpclk# interrupt at the next instruction retirement boundary, the processor performs the following actions, in the order shown: 1. its instruction pipelines are flushed 2. all pending and in-progress bus cycles are completed 3. the stpclk# assertion is acknowledged by executing a stop grant special bus cycle 4. its internal clock is stopped after brdy# of the stop grant special bus cycle is sampled asserted (if ewbe# is masked off, then entry into the stop grant state is not affected by ewbe#) and after ewbe# is sampled asserted 5. the stop clock state is entered if the system logic stops the bus clock clk (optional) stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. the system logic drives the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle. 16 8 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 75. stop grant and stop clock modes, part 1 stpclk# sampled asserted stop grant special cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy# stop clock a[4:3] = 10b fbh 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 169 figure 76. stop grant and stop clock modes, part 2 stop grant state (re-entered after pll stabilization) stpclk# sampled negated normal stop clock clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy# 170 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 init-initiated transition from protected mode to real mode init is typically asserted in response to a bios interrupt that writes to an i/o port. this interrupt is often in response to a ctrl-alt-del keyboard input. the bios writes to a port (similar to port 64h in the keyboard controller) that asserts init. init is also used to support 80286 software that must return to real mode after accessing extended memory in protected mode. the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0h the same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers (msrs), the cd and nw bits of the cr0 register, the time stamp counter, and other specific internal resources. figure 77 shows an example in which the operating system writes to an i/o port, causing the system logic to assert init. the sampling of init asserted starts an extended microcode sequence that terminates with a code fetch from ffff_fff0h, the reset location. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. if init is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 5 bus cycles 171 figure 77. init-initiated transition from protected mode to real mode code fetch ffff_fff0h init sampled asserted clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] ken# brdy# init 17 2 bus cycles chapter 5 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 6 power-on configuration and initialization 17 3 6 power-on configuration and initialization on power-on the system logic must reset the AMD-K6-III processor by asserting the reset signal. when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the mmx and 3dnow! states, and all registers. then the processor jumps to address ffff_fff0h to start instruction execution. 6.1 signals sampled during the falling transition of reset flush# flush# is sampled on the falling transition of reset to determine if the processor begins normal instruction execution or enters tri-state test mode. if flush# is high during the falling transition of reset, the processor unconditionally runs its built-in self test (bist), performs the normal reset functions, then jumps to address ffff_fff0h to start instruction execution. (see built-in self-test (bist) on page 223 for more details.) if flush# is low during the falling transition of reset, the processor enters tri-state test mode. (see tri-state test mode on page 224 and flush# (cache flush) on page 103 for more details.) bf[2:0] the internal operating frequency of the processor is determined by the state of the bus frequency signals bf[2:0] when they are sampled during the falling transition of reset. the frequency of the clk input signal is multiplied internally by a ratio defined by bf[2:0]. (see bf[2:0] (bus frequency) on page 92 for the processor-clock to bus-clock ratios.) 174 power-on configuration and initialization chapter 6 amd-k6 ? - iii processor data sheet 21918b/0october 1999 6.2 reset requirements during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification. ( see clk switching characteristics on page 267 for clock specifications. see electrical data on page 259 for v cc specifications.) during a warm reset while clk and v cc are within specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 state of processor after reset output signals table 29 shows the state of all processor outputs and bidirectional signals immediately after reset is sampled asserted. registers table 30 on page 175 shows the state of all architecture registers and model-specific registers (msrs) after the processor has completed its initialization due to the recognition of the assertion of reset. table 29. output signal state after reset signal state signal state a[31:3], ap floating lock# high ads#, adsc# high m/io# low apchk# high pcd low be[7:0]# floating pchk# high breq low pwt low cache# high scyc low d/c# low smiact# high d[63:0], dp[7:0] floating tdo floating ferr# high vcc2det low hit# high vcc2h/l# low hitm# high w/r# low hlda low CC 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 6 power-on configuration and initialization 17 5 table 30. register state after reset register state (hex) notes gdtr base:0000_0000h limit:0 ffffh idtr base:0000_0000h limit:0 ffffh tr 0000h ldtr 0000h eip ffff_fff0h eflags 0000_0002h eax 0000_0000h 1 ebx 0000_0000h ecx 0000_0000h edx 0000_059xh 2 esi 0000_0000h edi 0000_0000h ebp 0000_0000h esp 0000_0000h cs f000h ss 0000h ds 0000h es 0000h fs 0000h gs 0000h fpu stack r7Cr0 0000_0000_0000_0000_0000h 3 fpu control word 0040h 3 fpu status word 0000h 3 fpu tag word 5555h 3 fpu instruction pointer 0000_0000_0000h 3 fpu data pointer 0000_0000_0000h 3 fpu opcode register 000_0000_0000b 3 notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6- iii processor signature, where x indicates the processor stepping id. 3. the contents of these registers are preserved following the recognition of init. 4. the cd and nw bits of cr0 are preserved following the recognition of init 5. s represents the stepping. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset. 176 power-on configuration and initialization chapter 6 amd-k6 ? - iii processor data sheet 21918b/0october 1999 cr0 6000_0010h 4 cr2 0000_0000h cr3 0000_0000h cr4 0000_0000h dr7 0000_0400h dr6 ffff_0ff0h dr3 0000_0000h dr2 0000_0000h dr1 0000_0000h dr0 0000_0000h mcar 0000_0000_0000_0000h 3 mctr 0000_0000_0000_0000h 3 tr12 0000_0000_0000_0000h 3 tsc 0000_0000_0000_0000h 3 efer 0000_0000_0000_0002h 3 star 0000_0000_0000_0000h 3 whcr 0000_0000_0000_0000h 3 uwccr 0000_0000_0000_0000h psor 0000_0000_0000_01sbh 5 pfir 0000_0000_0000_0000h table 30. register state after reset (continued) register state (hex) notes notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6- iii processor signature, where x indicates the processor stepping id. 3. the contents of these registers are preserved following the recognition of init. 4. the cd and nw bits of cr0 are preserved following the recognition of init 5. s represents the stepping. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of reset. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 6 power-on configuration and initialization 17 7 6.4 state of processor after init the recognition of the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx and 3dnow! states, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. 178 power-on configuration and initialization chapter 6 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 179 7 cache organization the following sections describe the basic architecture and resources of the AMD-K6-III processor internal caches. the performance of the AMD-K6-III processor is enhanced by writeback level-one (l1) and level-two (l2) caches. the l1 cache is organized as separate 32-kbyte instruction and data caches, each with two-way set associativity. the l2 cache is 256 kbytes, and is organized as a unified, four-way set-associative cache (see figure 78 on page 180). the cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. as the l1 instruction cache is filled from the l2 cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecode logic. predecoding annotates each instruction byte in the l1 instruction cache with information that later enables the decoders to efficiently decode multiple instructions simultaneously. translation lookaside buffers (tlb) are used in conjunction with the l1 cache to translate linear addresses to physical addresses. the l1 instruction cache is associated with a 64-entry tlb while the l1 data cache is associated with a 128-entry tlb. 18 0 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 78. l1 and l2 cache organization processor core system bus interface unit 128-entry tlb 64-entry tlb state bit tag ram way 0 way 1 state bit tag ram 32-kbyte l1 instruction cache 32-kbyte l1 data cache pre-decode instruction cache mesi bits tag ram way 0 way 1 mesi bits tag ram 256-kbyte l2 cache mesi bits tag ram way 0 way 1 mesi bits tag ram mesi bits tag ram way 2 way 3 mesi bits tag ram 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 181 the processor cache design takes advantage of a sectored organization (see figure 79). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. l1 instruction cache line l1 data cache line and l2 cache line note: l1 instruction-cache lines have only two coherency states (valid or invalid) rather than the four mesi coherency states of l1 data-cache and l2 cache lines. only two states are needed for the l1 instruction cache because these lines are read-only. figure 79. l1 cache sector organization 7.1 mesi states in the l1 data cache and l2 cache the state of each line in the caches is tracked by the mesi bits. the coherency of these states or mesi bits is maintained by internal processor snoops and external inquire cycles by the system logic. the following four states are defined for the l1 data cache and the l2 cache: n modified this line has been modified and is different from external memory. n exclusive in general, an exclusive line in the l1 data cache or the l2 cache is not modified and is the same as external memory. the exception is the case where a line exists in the modified state in the l1 data cache and also resides in the l2 cache. by design, the line in the l2 cache must be in the exclusive state. n shared if a cache line is in the shared state it means that the same line can exist in more than one cache system. n invalid the information in this line is not valid. tag address cache line 0 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit tag address cache line 0 byte 31 byte 30 ........ ........ byte 0 2 mesi bits cache line 1 byte 31 byte 30 ........ ........ byte 0 2 mesi bits 182 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 7.2 predecode bits decoding x86 instructions is particularly difficult because the instructions vary in length, ranging from 1 to 15 bytes long. predecode logic supplies the predecode bits associated with each instruction byte. the predecode bits indicate the number of bytes to the start of the next x86 instruction. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. the predecode bits use memory separate from the 32-kbyte l1 instruction cache. the predecode bits are stored in an extended l1 instruction cache alongside each x86 instruction byte as shown in figure 79 on page 181. the l2 cache does not store predecode bits. as an instruction cache line is fetched from the l2 cache, the predecode bits are generated and stored alongside the cache line in the l1 instruction cache in the same manner as if the cache line were fetched from the processors system bus. 7.3 cache operation the operating modes for the caches are configured by software using the not writethrough (nw) and cache disable (cd) bits of control register 0 (cr0 bits 29 and 30, respectively). these bits are used in all operating modes. when the cd and nw bits are both set to 0, the cache is fully enabled. this is the standard operating mode for the cache. if a l1 cache read miss occurs, the processor determines if the read hits the l2 cache, in which case the cache line is supplied from the l2 cache to the l1 cache. if a read misses both the l1 and the l2 caches, a line fill (32-byte burst read) on the system bus occurs in order to fetch the cache line. the cache line is then filled in both the l1 and the l2 caches. write hits to the l1 and l2 caches are updated, while write misses and writes to shared lines cause external memory updates. refer to table 34 on page 195 for a summary of cache read and write cycles and the effect of these operations on the cache mesi state. note: a write allocate operation can modify the behavior of write misses to the caches. see write allocate on page 189. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 183 the AMD-K6-III processor does not enforce any rules of inclusion or exclusion as part of the protocol defined for the l1 and l2 caches. however, there are certain restrictions imposed by design on the allowable mesi states of a cache line that exists in both the l1 cache and the l2 cache. refer to table 35 on page 200 for a list of the valid cache-line states allowed. when cd is set to 0 and nw is set to 1, an invalid mode of operation exists that causes a general protection fault to occur. when cd is set to 1 (disabled) and nw is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. the processor reads from the caches if the read hits the l1 or the l2 cache. if a read misses both the l1 and the l2 caches, a line fill does not occur on the system bus. write hits to the l1 or l2 cache are updated, while write misses and writes to shared lines cause external memory updates. if pwt is driven low and wb/wt# is sampled high, a write hit to a shared line changes the cache-line state to exclusive. when the cd and nw bits are both set to 1, the cache is fully disabled. even though the cache is disabled, the contents are not necessarily invalid. the processor reads from the caches if the read hits the l1 or the l2 cache. if a read misses both the l1 and the l2 caches, a line fill does not occur on the system bus. if a write hits the l1 or the l2 cache, the cache is updated but an external memory update does not occur. if a cache line is in the exclusive state during a write hit, the cache-line state is changed to modified. cache lines in the shared state remain in the shared state after a write hit. write misses access external memory directly. the operating system can control the cacheability of a page. the paging mechanism is controlled by cr3, the page directory entry (pde), and the page table entry (pte). within cr3, pde, and pte are page cache disable (pcd) and page writethrough (pwt) bits. the values of the pcd and pwt bits used in table 31 and table 32 are taken from either the pte or pde. for more information see the descriptions of pcd and pwt on pages 113 and 115, respectively. 184 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 31 describes how the pwt signal is driven based on the values of the pwt bits and the pg bit of cr0. table 32 describes how the pcd signal is driven based on the values of the cd bit of cr0, the pcd bits, and the pg bit of cr0. table 33 describes how the cache# signal is driven based on the cycle type, the ci bit of tr12, the pcd signal, and the uwccr model-specific register. table 31. pwt signal generation pwt bit* pg bit of cr0 pwt signal 11high 01low 10low 00low note: * pwt is taken from pte or pde table 32. pcd signal generation cd bit of cr0 pcd bit* pg bit of cr0 pcd signal 1xxhigh 011high 001low 010low 000low note: * pcd is taken from pte or pde 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 185 cache-related signals complete descriptions of the signals that control cacheability and cache coherency are given on the following pages: n cache# page 96 n eads#page 100 n flush#page 103 n hit#page 104 n hitm#page 104 n invpage 108 n ken#page 109 n pcdpage 113 n pwtpage 115 n wb/wt#page 123 7.4 cache disabling and flushing l1 and l2 cache disabling to completely disable all accesses to the l1 and the l2 caches, the cd bit must be set to 1 and the caches must be completely flushed. there are three different methods for flushing the caches. the first method relies on the system logic and the other two methods rely on software. for the system logic to flush the caches, the processor must sample flush# asserted. in this method, the processor writes back any l1 data cache and l2 cache lines that are in the table 33. cache# signal generation cycle type ci bit of tr12 pcd signal access within wc/uc range* cache# writebacks x x x low unlocked reads 0 0 0 low locked reads x x x high single writes x x x high any cycle except writebacks 1 x x high any cycle except writebacks x 1 x high any cycle except writebacks x x 1 high note: * wc and uc refer to write-combining and uncacheable memory ranges as defined in the uwccr. 18 6 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 modified state, invalidates all lines in all caches, and then executes a flush acknowledge special cycle (see table 23 on page 126). the second method for flushing the caches is for software to execute the wbinvd instruction which causes all modified lines to first be written back to memory, then marks all cache lines as invalid. alternatively, if writing modified lines back to memory is not necessary, the invd instruction can be used to invalidate all cache lines. the third and final method for flushing the caches is to make use of the page flush/invalidate register (pfir), which allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space (see pfir on page 198). unlike the previous two methods of flushing the caches, this particular method requires the software to be aware of which specific pages must be flushed and invalidated. l2 cache disabling the l2 cache in the AMD-K6-III processor can be completely disabled by setting the l2 disable (l2d) bit (efer[4]) to 1 (see extended feature enable register (efer) on page 39). if disabled in this manner, the processor does not access the l2 cache for any purpose, including allocations, read hits, write hits, snoops, inquire cycles, flushing, and read/write attempts by means of the l2aar. (see l2 cache and tag array testing on page 186.) the l1 cache operation is not affected by disabling the l2 cache. the l2d bit is provided for debug and testing purposes only. for normal operation and maximum performance, this bit must be set to 0, which is the default setting following reset. the AMD-K6-III processor does not provide a method for disabling the l1 cache while the l2 cache remains enabled. 7.5 l2 cache and tag array testing the AMD-K6-III processor provides the l2aar msr that allows for direct access to the l2 cache and l2 tag arrays. for more detailed information, refer to l2 cache and tag array testing on page 237. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 187 7.6 cache-line fills the processor performs a cache-line fill for any area of system memory defined as cacheable. if an area of system memory is not explicitly defined as uncacheable by the software or system logic, or implicitly treated as uncacheable by the processor, then the memory access is assumed to be cacheable. software can prevent caching of certain pages by setting the pcd bit in the pde or pte. additionally, software can define regions of memory as uncacheable or write combinable by programming the mtrrs in the uwccr msr (see memory type range registers on page 205). write-combinable memory is defined as uncacheable. the system logic also has control of the cacheability of bus cycles. if it determines the address is not cacheable, system logic negates the ken# signal when asserting the first brdy# or na# of a cycle. the processor does not cache certain memory accesses such as locked operations. in addition, the processor does not cache pde or pte memory reads in the l1 cache (referred to as page table walks ). however, page table walks are cached in the l2 cache if the pde or pte is determined to be cacheable. when the processor needs to read memory, the processor drives a read cycle onto the bus. if the cycle is cacheable, the processor asserts cache#. if the cycle is not cacheable, a non-burst, single-transfer read takes place. the processor waits for the system logic to return the data and assert a single brdy# (see figure 56 on page 133). if the cycle is cacheable, the processor executes a 32-byte burst read cycle. the processor expects a total of four brdy# signals for a burst read cycle to take place (see figure 58 on page 137). cache-line fills initiate 32-byte burst read cycles from memory on the system bus for the l1 instruction cache and the l1 data cache. all l1 cache-line fills supplied from the system bus are also filled in the l2 cache. 18 8 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 7.7 cache-line replacements as programs execute and task switches occur, some cache lines eventually require replacement. when a cache miss occurs in the l1 cache, the required cache line is filled from either the l2 cache, if the cache line is present (l2 cache hit), or from external memory, if the cache line is not present (l2 cache miss). if the cache line is filled from external memory, the cache line is filled in both the l1 and the l2 caches. two forms of cache misses and associated cache fills can take placea tag-miss cache fill and a tag-hit cache fill. in the case of a tag-miss cache fill, the level-one cache miss is due to a tag mismatch, in which case the required cache line is filled either from the level-two cache or from external memory, and the level-one cache line within the sector that was not required is marked as invalid. in the case of a tag-hit cache fill, the address matches the tag, but the requested cache line is marked as invalid. the required level-one cache line is filled from the level-two cache or from external memory, and the level-one cache line within the sector that is not required remains in the same cache state. if a l1 data-cache line being filled replaces a modified line, the modified line is written back to the l2 cache if the cache line is present (l2 cache hit). by design, if a cache line is in the modified state in the l1 cache, this cache line can only exist in the l2 cache in the exclusive state. during the writeback, the l2 cache-line state is changed from exclusive to modified, and the writeback does not occur on the system bus. if the replacement writeback does not hit the l2 cache (l2 cache miss), then the modified l1 cache line is written back on the system bus, and the l2 cache is not updated. if the other cache line in this sector is in the modified state, it is also written back in the same manner. l1 instruction-cache lines and l2 cache lines are replaced using a least recently used (lru) algorithm. if a line replacement is required, lines are replaced when read cache misses occur. the l1 data cache uses a slightly different approach to line replacement. if a miss occurs, and a replacement is required, lines are replaced by using a least recently allocated (lra) algorithm. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 189 7.8 write allocate write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 data cache. if the line does not exist in the l2 cache, the processor performs a 32-byte burst read cycle on the system bus to fetch the data-cache line addressed by the pending write cycle. if the line does exist in the l2 cache, the data is supplied directly from the l2 cache, in which case a system bus cycle is not executed. the data associated with the pending write cycle is merged with the recently-allocated data-cache line and stored in the processors l1 data cache. if the data-cache line was fetched from memory (because of a l2 cache miss), the data is stored, without modification, in the l2 cache. the final mesi state of the cache lines depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent l1 data cache write hit (see table 34 on page 195 to determine the cache-line states and the access types following a cache write miss). if the l1 data cache line is stored in the modified state, then the same cache line is stored in the l2 cache in the exclusive state. if the l1 data cache line is stored in the shared state, then the same cache line is stored in the l2 cache in the shared state. if a data-cache line fetch from memory is attempted because the write allocate misses the l2 cache, and ken# is sampled negated, the processor does not perform an allocation. in this case, the pending write cycle is executed as a single write cycle on the system bus. during write allocates that miss the l2 cache, a 32-byte burst read cycle is executed in place of a non-burst write cycle. while the burst read cycle generally takes longer to execute than the non-burst write cycle, performance gains are realized on subsequent write cycle hits to the write-allocated cache line. due to the nature of software, memory accesses tend to occur in proximity of each other (principle of locality). the likelihood of additional write hits to the write-allocated cache line is high. write allocates that hit the l2 cache increase performance by avoiding accesses to the system bus. the following is a description of three mechanisms by which the AMD-K6-III processor performs write allocations. a write allocate is performed when any one or more of these mechanisms indicates that a pending write is to a cacheable area of memory. 19 0 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 write to a cacheable page every time the processor completes a l1 cache line fill, the address of the page in which the cache line resides is saved in the cacheability control register (ccr). the page address of subsequent write cycles is compared with the page address stored in the ccr. if the two addresses are equal, then the processor performs a write allocate because the page has already been determined to be cacheable. when the processor performs a l1 cache line fill from a different page than the address saved in the ccr, the ccr is updated with the new page address. write to a sector if the address of a pending write cycle matches the tag address of a valid l1 cache sector, but the addressed cache line within the sector is marked invalid (a sector hit but a cache line miss), then the processor performs a write allocate. the pending write cycle is determined to be cacheable because the sector hit indicates the presence of at least one valid cache line in the sector. the two cache lines within a sector are guaranteed by design to be within the same page. write allocate limit the AMD-K6-III processor uses two mechanisms that are programmable within the write handling control register (whcr) to enable write allocations for write cycles that address a definable area, or a special 1-mbyte memory area. the w hcr contains two fieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 80). figure 80. write handling control register (whcr) 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 191 write allocate enable limit. the waelim field is 10 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. the maximum value of this limit is ((2 10 C1) 4 mbytes) = 4092 mbytes. when all the bits in this field are set to 0, all memory is above this limit and write allocates due to this mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). write allocate enable 15-to-16-mbyte. the write allocate enable 15-to-16-mbyte (wae15m) bit is used to enable write allocations for memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocate in this memory area. this bit is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition a write allocate is not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. it is not considered safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. if a memory region is defined as write combinable or uncacheable by a mtrr, write allocates are not performed in that region. 192 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 write allocate logic mechanisms and conditions figure 81 shows the logic flow for all the mechanisms involved with write allocate for memory bus cycles. the left side of the diagram (the text) describes the conditions that need to be true in order for the value of that line to be a 1. items 1 to 4 of the diagram are related to general cache operation and items 5 to 10 are related to the write allocate mechanisms. for more information about write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326. figure 81. write allocate logic mechanisms and conditions the following list describes the corresponding items in figure 81: 1. cd bit of cr0 when the cache disable (cd) bit within control register 0 (cr0) is set to 1, the cache fill mechanism for both reads and writes is disabled and write allocate does not occur. 2. pcd signal when the pcd (page cache disable) signal is driven high, caching for that page is disabled, even if ken# is sampled asserted, and write allocate does not occur. 3. ci bit of tr12 when the cache inhibit bit of test register 12 is set to 1, l1 and l2 cache fills are disabled and write allocate does not occur. 4. uc or wc if a pending write cycle addresses a region of memory defined as write combinable or uncacheable by an mtrr, write allocates are not performed in that region. 1) cd bit of cr0 perform write allocate 3) ci bit of tr12 2) pcd signal 5) write to cacheable page (ccr) 6) write to a sector 8) between 640 kbytes and 1 mbyte 7) less than limit (waelim) 9) between 15C16 mbytes 10) write allocate enable 15C16 mbyte (wae15m) 4) uc or wc 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 193 5. write to a cacheable page (ccr) a write allocate is performed if the processor knows that a page is cacheable. the ccr is used to store the page address of the last l1 cache fill for a read miss. see write to a cacheable page on page 190 for a detailed description of this condition. 6. write to a sector a write allocate is performed if the address of a pending write cycle matches the tag address of a valid l1 cache sector but the addressed cache line within the sector is invalid. see write to a sector on page 190 for a detailed description of this condition. 7. less than limit (waelim) the write allocate limit mechanism determines if the memory area being addressed is less than the limit set in the waelim field of whcr. if the address is less than the limit, write allocate for that memory address is performed as long as conditions 8 through 10 do not prevent write allocate (even if conditions 8 and 10 attempt to prevent write allocate, condition 5 or 6 allows write allocate to occur). 8. between 640 kbytes and 1 mbyte write allocate is not performed in the memory area between 640 kbytes and 1 mbyte. it is not considered safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because this area of memory is considered a noncacheable region of memory (even if condition 8 attempts to prevent write allocate, condition 5 or 6 allows write allocate to occur). 9. between 15C16 mbytes if the address of a pending write cycle is in the 1 mbyte of memory between 15 mbytes and 16 mbytes, and the wae15m bit is set to 1, write allocate for this cycle is enabled. 10. write allocate enable 15C16 mbytes (wae15m) this condition is associated with the write allocate limit mechanism and affects write allocate only if the limit specified by the waelim field is greater than or equal to 16 mbytes. if the memory address is between 15 mbytes and 16 mbytes, and the wae15m bit in the whcr is set to 0, write allocate for this cycle is disabled (even if condition 10 attempts to prevent write allocate, condition 5 or 6 allows write allocate to occur). 194 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 7.9 prefetching hardware prefetching the AMD-K6-III processor conditionally performs cache prefetching which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. from the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. the burst read cycles do not occur back-to-back (wait states occur) if the processor is not ready to start a new cycle, if higher priority data read or write requests exist, or if na# (next address) was sampled negated. wait states can also exist between burst cycles if the processor samples ahold or boff# asserted. software prefetching the 3dnow! technology includes an instruction called prefetch that allows a cache line to be prefetched into the l1 data cache and the l2 cache. unlike prefetching under hardware control, software prefetching only fetches the cache line specified by the operand of the prefetch instruction, and does not attempt to fetch the other cache line in the sector. the prefetch instruction format is defined in table 15, 3dnow!? instructions, on page 81. for more detailed information, see the 3dnow!? technology manual , order# 21928. 7.10 cache states table 34 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 195 table 34. l1 and l2 cache states for read and write accesses type cache state before access 4 access type cache state after access mesi state 1 l1 l2 l1 l2 cache read read miss l1, read miss l2 i i single read from bus i i i i burst read from bus, fill l1 and l2 2 s or e 3 s or e 3 read hit l1 e CCeC sC C sC mC C mC read miss l1, read hit l2 i e fill l1 e e i s fill l1 s s i m fill l1 m e i m fill l1 e 9 m 9 notes: 1. the final mesi state assumes that the state of the wb/wt# signal remains the same for all accesses to a particular cache line. 2. if cache# is driven low and ken# is sampled asserted. 3. if pwt is driven low and wb/wt# is sampled high, the line is cached in the exclusive (writeback) state. if pwt is driven high or wb/wt# is sampled low, the line is cached in the shared (writethrough) state. 4. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruction cache and are treated as valid states. 5. assumes the write allocate conditions as specified in write allocate on page 189 are not met. 6. assumes the write allocate conditions as specified in write allocate on page 189 are met. 7. assumes pwt is driven low and wb/wt# is sampled high. 8. assumes pwt is driven high or wb/wt# is sampled low. 9. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 data cache and in the modified state in the l2 cache. C not applicable or none. 19 6 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 cache write write miss l1 write miss l2 ii single write to bus 5 ii ii burst read from bus, fill l1 and l2, write to l1 6 m 7 e 7 ii burst read from bus, fill l1 and l2, write to l1 and l2, single write to bus 6 s 8 s 8 write hit l1 si write to l1, single write to bus s or e 3 i ss write to l1 and l2, single write to bus s or e 3 s or e 3 e or m C write to l1 m C write miss l1 write hit l2 ie write to l2 5 im is write to l2, single write to bus 5 i s or e 3 im write to l2 5 im ie fill l1, write to l1 6 me is write to l2, single write to bus 6 s or e 3 s or e 3 im fill l1, write to l1 6 me table 34. l1 and l2 cache states for read and write accesses (continued) type cache state before access 4 access type cache state after access mesi state 1 l1 l2 l1 l2 notes: 1. the final mesi state assumes that the state of the wb/wt# signal remains the same for all accesses to a particular cache line. 2. if cache# is driven low and ken# is sampled asserted. 3. if pwt is driven low and wb/wt# is sampled high, the line is cached in the exclusive (writeback) state. if pwt is driven high or wb/wt# is sampled low, the line is cached in the shared (writethrough) state. 4. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruction cache and are treated as valid states. 5. assumes the write allocate conditions as specified in write allocate on page 189 are not met. 6. assumes the write allocate conditions as specified in write allocate on page 189 are met. 7. assumes pwt is driven low and wb/wt# is sampled high. 8. assumes pwt is driven high or wb/wt# is sampled low. 9. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 data cache and in the modified state in the l2 cache. C not applicable or none. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 197 7.11 cache coherency different ways exist to maintain coherency between the system memory and cache memories. inquire cycles, internal snoops, flush#, wbinvd, invd, and line replacements all prevent inconsistencies between memories. inquire cycles inquire cycles are bus cycles initiated by system logic which ensure coherency between the caches and main memory. in systems with multiple bus masters, system logic maintains cache coherency by driving inquire cycles to the processor. system logic initiates inquire cycles by asserting ahold, boff#, or hold to obtain control of the address bus and then driving eads#, inv (optional), and an inquire address (a[31:5]). this type of bus cycle causes the processor to compare the tags for its l1 instruction and l1 data caches, and l2 cache, with the inquire address. if there is a hit to a shared or exclusive line in the l1 data cache or the l2 cache, or a valid line in the l1 instruction cache, the processor asserts hit#. if the compare hits a modified line in the l1 data cache or the l2 cache, the processor asserts hit# and hitm#. if hitm# is asserted, the processor writes the modified line back to memory. if inv was sampled asserted with eads#, a hit invalidates the line. if inv was sampled negated with eads#, a hit leaves the line in the shared state or transitions it from the exclusive or modified state to the shared state. table 35 on page 200 lists valid combinations of mesi states permitted for a cache line in the l1 and l2 caches, and shows the effects of inquire cycles performed with inv equal to 0 (non-invalidating) and inv equal to 1 (invalidating). internal snooping internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. it is used to maintain coherency between the l1 instruction cache and the l1 data cache. the processor automatically snoops its l1 instruction cache during read or write misses to its l1 data cache, and it snoops its l1 data cache during read misses to its l1 instruction cache. the l2 cache is not snooped during misses to either of the l1 caches. table 36 on page 201 summarizes the actions taken during this internal snooping. 19 8 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 if an internal snoop hits its target, the processor does the following: n l1 data cache snoop during a l1 i nstruction-cache read miss if modified, the line in the l1 data cache is written back. if the writeback hits the l2 cache, the cache line is stored in the l2 cache in the modified state and no writeback occurs on the system bus. if the writeback misses the l2 cache, the cache line is written back on the system bus to external memory. regardless of its state, the l1 data-cache line is invalidated and the l1 instruction cache performs a read from either the l2 cache (if a l2 hit occurs) or external memory (if a l2 miss occurs). n l1 instruction cache snoop during a l1 data cache miss the line in the instruction cache is marked invalid, and the l1 data-cache read or write is performed as defined in table 34 on page 195. flush# in response to sampling flush# asserted, the processor writes back any l1 data cache lines and l2 cache lines that are in the modified state and then marks all lines in the l1 instruction cache, the l1 data cache, and the l2 cache as invalid. pfir the AMD-K6-III processor contains the page flush/invalidate register (pfir) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space (see figure 82). when the pfir is written to (using the wrmsr instruction), the invalidation and, optionally, the flushing begins. the total amount of cache in the AMD-K6-III processor is 320 kbytes. using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. figure 82. page flush/invalidate register (pfir)msr c000_0088h linpage 10 63 f / i reserved symbol description bit linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 199 linpage. this 20-bit field must be written with bits 31:12 of the linear address of the 4-kbyte page that is to be invalidated and optionally flushed from the l1 or the l2 cache. pf. if an attempt to invalidate or flush a page results in a page fault, the processor sets the pf bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). in this case, an actual page fault exception is not generated. if the pf bit equals 0 after an invalidate or flush operation, then the operation executed successfully. the pf bit must be read after every write to the pfir register to determine if the invalidate or flush operation executed successfully. f/i. this bit is used to control the type of action that occurs to the specified linear page. if a 0 is written to this bit, the operation is a flush, in which case all cache lines in the modified state within the specified page are written back to memory, after which the entire page is invalidated. if a 1 is written to this bit, the operation is an invalidation, in which case the entire page is invalidated without the occurrence of any writebacks. wbinvd and invd these x86 instructions cause all cache lines to be marked as invalid. wbinvd writes back modified lines before marking all cache lines invalid. invd does not write back modified lines. cache-line replacement replacing lines in the l1 cache and the l2 cache, according to the line replacement algorithms described in cache-line fills on page 187, ensures coherency between external memory and the caches. table 36 on page 201 shows all possible cache-line states before and after various cache-related operations. 200 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 35. valid l1 and l2 cache states and effect of inquire cycles cache state before inquire 1 memory access 2 cache state after inquire inv = 0 inv = 1 l1 l2 l1 l2 l1 l2 i m writeback l2 to bus i s i i ie Cisii is C isi i ii C iiii e 3 m 3 writeback l2 to bus s s i i ee C ss i i ei C siii m e writeback l1 to bus s i i i m i writeback l1 to bus s i i i ss C ss i i si C siii notes: 1. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruction cache and are treated as valid states. 2. writeback cycles to the bus are 32-byte burst writes. 3. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 data cache and in the modified state in the l2 cache. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 7 cache organization 201 table 36. l1 and l2 cache states for snoops, flushes, and invalidation type of operation cache state before operation 1 access type 2 cache state after operation l1 l2 l1 l2 internal snoop im Cim ie C ie is C is ii C ii e 3 m 3 Cim ee C i e ei C i i m e writeback l1 to l2 i m m i writeback l1 to bus i i ss C i s si C i i flush# signal s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i pfir (f/i = 0) s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i pfir (f/i = 1) CC C i i wbinvd instruction s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i invd instruction CC C i i notes: 1. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruction cache and are treated as valid states. 2. writeback cycles to the bus are 32-byte burst writes. 3. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 data cache and in the modified state in the l2 cache. C not applicable or none. 202 cache organization chapter 7 amd-k6 ? - iii processor data sheet 21918b/0october 1999 7.12 writethrough versus writeback coherency states the terms writethrough and writeback apply to two related concepts in a read-write cache like the AMD-K6-III processor l1 data cache and the l2 cache. the following conditions apply to both the writethrough and writeback modes: n memory writes a relationship exists between external memory writes and their concurrence with cache updates: ? an external memory write that occurs concurrently with a cache update to the same location is a writethrough. writethroughs are driven as single cycles on the bus. ? an external memory write that occurs after the processor has modified a cache line is a writeback. writebacks are driven as burst cycles on the bus. n coherency state a relationship exists between mesi coherency states and writethrough-writeback coherency states of lines in the cache as follows: ? shared and invalid mesi lines are in the writethrough state. ? modified and exclusive mesi lines are in the writeback state. 7.13 a20m# masking of cache accesses although the processor samples a20m# as a level-sensitive input on every clock edge, it should only be asserted in real mode. the processor applies the a20m# masking to its tags, through which all programs access the caches. therefore, assertion of a20m# affects all addresses (cache and external memory), including the following: n cache-line fills (caused by read misses or write allocates) n cache writethroughs (caused by write misses or write hits to lines in the shared state) however, a20m# does not mask writebacks or invalidations caused by the following actions: n internal snoops n inquire cycles n the flush# signal n writing to the pfir n the wbinvd instruction 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 8 write merge buffer 203 8 write merge buffer the AMD-K6-III processor contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge buffer. the merge buffer operates in conjunction with the memory type range registers (mtrrs). refer to memory type range registers on page 205 for a description of the mtrrs. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. 8.1 ewbe control the presence of the merge buffer creates the potential to perform out-of-order write cycles relative to the processors caches. in general, the ordering of write cycles that are driven externally on the system bus and those that hit the processors cache can be controlled by the ewbe# signal. see ewbe# (external write buffer empty) on page 101 for more information. if ewbe# is sampled negated, the processor delays the commitment of write cycles to cache lines in the modified state or exclusive state in the processors caches. therefore, the system logic can enforce strong ordering by negating ewbe# until the external write cycle is complete, thereby ensuring that a subsequent write cycle that hits a cache does not complete ahead of the external write cycle. however, the addition of the write merge buffer introduces the potential for out-of-order write cycles to occur between writes to the merge buffer and writes to the processors caches. because these writes occur entirely within the processor and are not sent out to the processor bus, the system logic is not able to enforce strong ordering with the ewbe# signal. the ewbe control (ewbec) bits in the efer register provide a mechanism for enforcing three different levels of write ordering in the presence of the write merge buffer: n efer[3] is defined as the global ewbe disable (gewbed). when gewbed equals 1, the processor does not attempt to enforce any write ordering internally or externally (the ewbe# signal is ignored). this is the maximum performance setting. 204 write merge buffer chapter 8 amd-k6 ? - iii processor data sheet 21918b/0october 1999 n efer[2] is defined as the speculative ewbe disable (sewbed). sewbed only affects the processor when gewbed equals 0. if gewbed equals 0 and sewbed equals 1, the processor enforces strong ordering for all internal write cycles with the exception of write cycles addressed to a range of memory defined as uncacheable (uc) or write-combining (wc) by the mtrrs. in addition, the processor samples the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting provides performance comparable to, but slightly less than, the performance obtained when gewbed equals 1 because some degree of write ordering is maintained. n if gewbed equals 0 and sewbed equals 0, the processor enforces strong ordering for all internal and external write cycles. in this setting, the processor assumes, or speculates , that strong order must be maintained between writes to the merge buffer and writes that hit the processors caches. once the merge buffer is written out to the processors bus, the ewbe# signal is sampled. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting is the default after reset and provides the lowest performance of the three settings because full write ordering is maintained. table 37 summarizes the three settings of the ewbec field for the efer register, along with the effect of write ordering and performance. for more information on the efer register, see extended feature enable register (efer) on page 39. table 37. ewbec settings efer[3] (gewbed) efer[2] (sewbed) write ordering performance 1 0 or 1 none best 0 1 all except uc/wc close-to-best 0 0 all slowest 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 8 write merge buffer 205 8.2 memory type range registers the AMD-K6-III processor provides two variable-range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as one of the following memory types: n uncacheable (uc) memorymemory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. memory write cycles are targeted at the specified memory address and a write allocation does not occur. n write-combining (wc) memorymemory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. the processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. this memory type is applicable for linear video frame buffers. uc/wc cacheability control register (uwccr) the mtrrs are accessed by addressing the 64-bit msr known as the uc/wc cacheability control register (uwccr). the msr address of the uwccr is c000_0085h. following reset, all bits in the uwccr register are set to 0. mtrr0 (lower 32 bits of the uwccr register) defines the size and memory type of range 0 and mtrr1 (upper 32 bits) defines the size and memory type of range 1 (see figure 83). 206 write merge buffer chapter 8 amd-k6 ? - iii processor data sheet 21918b/0october 1999 . figure 83. uc/wc cacheability control register (uwccr) msr c000_0085h (model 8/[f:8]) physical base address n (n=0, 1). this address is the 15 most- significant bits of the physical base address of the memory range. the least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-kbyte boundary. physical address mask n (n=0, 1). this value is the 15 most- significant bits of a physical address mask that is used to define the size of the memory range. this mask is logically anded with both the physical base address field of the uwccr register and the physical address generated by the processor. if the results of the two and operations are equal, then the generated physical address is considered within the range. that is, if: mask & physical base address = mask & physical address generated then the physical address generated by the processor is in the range. wcn (n=0, 1). when set to 1, this memory range is defined as write combinable (refer to table 38). write-combinable memory is uncacheable. ucn (n=0, 1). when set to 1, this memory range is defined as uncacheable (refer to table 38). 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 8 write merge buffer 207 memory-range restrictions. the following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the uwccr register: n the minimum size of each range is 128 kbytes. n the physical base address must be aligned on a 128-kbyte boundary. n the physical base address must be range-size aligned . for example, if the size of the range is 1 mbyte, then the physical base address must be aligned on a 1-mbyte boundary. n all bits set to 1 in the physical address mask must be contiguous. likewise, all bits set to 0 in the physical address mask must be contiguous. for example: 111_1111_1100_0000b is a valid physical address mask 111_1111_1101_0000b is invalid table 39 lists the valid physical address masks and the resulting range sizes that can be programmed in the uwccr register. table 38. wc/uc memory type wcn ucn memory type 0 0 no effect on cacheability or write combining 1 0 write-combining memory range (uncacheable) 0 or 1 1 uncacheable memory range table 39. valid masks and range sizes masks size 111_1111_1111_1111b 128 kbytes 111_1111_1111_1110b 256 kbytes 111_1111_1111_1100b 512 kbytes 111_1111_1111_1000b 1 mbyte 111_1111_1111_0000b 2 mbytes 111_1111_1110_0000b 4 mbytes 111_1111_1100_0000b 8 mbytes 208 write merge buffer chapter 8 amd-k6 ? - iii processor data sheet 21918b/0october 1999 example. suppose that the range of memory from 16 mbytes to 32 mbytes is uncacheable, and the 8-mbyte range of memory on top of 1 gbyte is write-combinable. range 0 is defined as the uncacheable range, and range 1 is defined as the write- combining range. extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 16 mbytes (0100_0000h) yields a physical base address 0 field of 000_0000_1000_0000b. because the uncacheable range size is 16 mbytes, the physical mask value 0 field is 111_1111_1000_0000b, according to table 39. bit 1 of the uwccr register (wc0) is set to 0 and bit 0 of the uwccr register is set to 1 (uc0). extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 gbyte (4000_0000h) yields a physical base address 1 field of 010_0000_0000_0000b. because the write-combining range size is 8 mbytes, the physical mask value 1 field is 111_1111_1100_0000b, according to table 39. bit 33 of the uwccr register (wc1) is set to 1 and bit 32 of the uwccr register is set to 0 (uc1). 111_1111_1000_0000b 16 mbytes 111_1111_0000_0000b 32 mbytes 111_1110_0000_0000b 64 mbytes 111_1100_0000_0000b 128 mbytes 111_1000_0000_0000b 256 mbytes 111_0000_0000_0000b 512 mbytes 110_0000_0000_0000b 1 gbyte 100_0000_0000_0000b 2 gbytes 000_0000_0000_0000b 4 gbytes table 39. valid masks and range sizes (continued) masks size 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 9 floating-point and multimedia execution units 209 9 floating-point and multimedia execution units 9.1 floating-point execution unit the AMD-K6-III processor contains an ieee 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. floating-point software is typically written to manipulate numbers that are very large or very small, that require a high degree of precision, or that result from complex mathematical operations such as transcendentals. applications that take advantage of floating-point operations include geometric calculations for graphics acceleration, scientific, statistical, and engineering applications, and business applications that use large amounts of high-precision data. the high-performance floating-point execution unit contains an adder unit, a multiplier unit, and a divide/square root unit. these low-latency units can execute floating-point instructions in as few as two processor clocks. to increase performance, the processor is designed to simultaneously decode most floating-point instructions with most short-decodeable instructions. see software environment on page 21 for a description of the floating-point data types, registers, and instructions. handling floating-point exceptions the AMD-K6-III processor provides the following two types of exception handling for floating-point exceptions: n if the numeric error (ne) bit in cr0 is set to 1, the processor invokes the interrupt 10h handler. in this manner, the floating-point exception is completely handled by software. n if the ne bit in cr0 is set to 0, the processor requires external logic to generate an interrupt on the intr signal in order to handle the exception. external logic support of floating-point exceptions the processor provides the ferr# (floating-point error) and ignne# (ignore numeric error) signals to allow the external logic to generate the interrupt in a manner consistent with ibm-compatible pc/at systems. the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point 210 floating-point and multimedia execution units chapter 9 amd-k6 ? - iii processor data sheet 21918b/0october 1999 instruction. ignne# is used by the external hardware to control the effect of an unmasked floating-point exception. under certain circumstances, if ignne# is sampled asserted, the processor ignores the floating-point exception. figure 84 illustrates an implementation of external logic for supporting floating-point exceptions. the following example explains the operation of the external logic in figure 84: as the result of a floating-point exception, the processor asserts ferr#. the assertion of ferr# and the sampling of ignne# negated indicates the processor has stopped instruction execution and is waiting for an interrupt. the assertion of ferr# leads to the assertion of intr by the interrupt controller. the processor acknowledges the interrupt and jumps to the corresponding interrupt service routine in which an i/o write cycle to address port f0h leads to the assertion of ignne#. when ignne# is sampled asserted, the processor ignores the floating-point exception and continues instruction execution. when the processor negates ferr#, the external logic negates ignne#. see ferr# (floating-point error) on page 102 and ignne# (ignore numeric exception) on page 106 for more details. figure 84. external logic for supporting floating-point exceptions ferr# flip-flop clock q data q clear irq13 interrupt controller i/o address port f0h amd-k6 ? - iii processor ferr# intr ignne# reset 1 ignne# flip-flop clock q data q clear 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 9 floating-point and multimedia execution units 211 9.2 multimedia and 3dnow!? execution units the multimedia and 3dnow! execution units of the AMD-K6-III processor are designed to accelerate the performance of software written using the industry-standard mmx instructions and the new 3dnow! instructions. applications that can take advantage of the mmx and 3dnow! instructions include graphics, video and audio compression and decompression, speech recognition, and telephony applications. the multimedia execution unit can execute mmx instructions in a single processor clock. all mmx and 3dnow! arithmetic instructions are pipelined for higher performance. to increase performance, the processor is designed to simultaneously decode all mmx and 3dnow! instructions with most other instructions. for more information on mmx instructions, see the amd-k6 ? processor multimedia technology manual , order# 20726. for more information on 3dnow! instructions, see the 3dnow!? technology manual , order# 21928. 9.3 floating-point and mmx?/3dnow!? instruction compatibility registers the eight 64-bit mmx registers (which are also utilized by 3dnow! instructions) are mapped on the floating-point stack. this enables backward compatibility with all existing software. for example, the register saving event that is performed by operating systems during task switching requires no changes to the operating system. the same support provided in an operating systems interrupt 7 handler (device not available) for saving and restoring the floating-point registers also supports saving and restoring the mmx registers. exceptions there are no new exceptions defined for supporting the mmx and 3dnow! instructions. all exceptions that occur while decoding or executing an mmx or 3dnow! instruction are handled in existing exception handlers without modification. ferr# and ignne# mmx instructions and 3dnow! instructions do not generate floating-point exceptions. however, if an unmasked floating-point exception is pending, the processor asserts ferr# at the instruction boundary of the next floating-point 212 floating-point and multimedia execution units chapter 9 amd-k6 ? - iii processor data sheet 21918b/0october 1999 instruction, mmx instruction, 3dnow! instruction or wait instruction. the sampling of ignne# asserted only affects processor operation during the execution of an error-sensitive floating-point instruction, mmx instruction, 3dnow! instruction or wait instruction when the ne bit in cr0 is set to 0. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 10 system management mode (smm) 213 10 system management mode (smm) 10.1 overview smm is an alternate operating mode entered by way of a system management interrupt (smi#) and handled by an interrupt service routine. smm is designed for system control activities such as power management. these activities appear transparent to conventional operating systems like dos and windows. smm is targeted for use by the basic input output system (bios), specialized low-level device drivers, and the operating system. the code and data for smm are stored in the smm memory area, which is isolated from main memory. the processor enters smm by the assertion of the smi# interrupt and the processors acknowledgment by the assertion of smiact#. at this point the processor saves its state into the smm memory state-save area and jumps to the smm service routine. the processor returns from smm when it executes the rsm (resume) instruction from within the smm service routine. subsequently, the processor restores its state from the smm save area, negates smiact#, and resumes execution with the instruction following the point where it entered smm. the following sections summarize the smm state-save area, entry into and exit from smm, exceptions and interrupts in smm, memory allocation and addressing in smm, and the smi# and smiact# signals. 10.2 smm operating mode and default register values the software environment within smm has the following characteristics: n addressing and operation in real mode n 4-gbyte segment limits n default 16-bit operand, address, and stack sizes, although instruction prefixes can override these defaults n control transfers that do not override the default operand size truncate the eip to 16 bits 214 system management mode (smm) chapter 10 amd-k6 ? - iii processor data sheet 21918b/0october 1999 n far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits, as in real mode segment-base addressing n a20m# is masked n interrupt vectors use the real-mode interrupt vector table n the if flag in eflags is cleared (intr not recognized) n the tf flag in eflags is cleared n the nmi and init interrupts are disabled n debug register dr7 is cleared (debug traps disabled) figure 85 shows the default map of the smm memory area. it consists of a 64-kbyte area, between 0003_0000h and 0003_ffffh, of which the top 32 kbytes (0003_8000h to 0003_ffffh) must be populated with ram. the default code-segment (cs) base address for the areacalled the smm base addressis at 0003_0000h. the top 512 bytes (0003_fe00h to 0003_ffffh) contain a fill-down smm state-save area. the default entry point for the smm service routine is 0003_8000h. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 10 system management mode (smm) 215 figure 85. smm memory table 40 shows the initial state of registers when entering smm. smm state-save area smm base address (cs) service routine entry point fill down smm service routine 32-kbyte minimum ram 0003_8000h 0003_fe00h 0003_ffffh 0003_0000h table 40. initial state of registers in smm registers smm initial state general purpose registers unmodified eflags 0000_0002h cr0 pe, em, ts, and pg are cleared (bits 0, 2, 3, and 31). the other bits are unmodified. dr7 0000_0400h gdtr, ldtr, idtr, tssr, dr6 unmodified eip 0000_8000h cs 0003_0000h ds, es, fs, gs, ss 0000_0000h 216 system management mode (smm) chapter 10 amd-k6 ? - iii processor data sheet 21918b/0october 1999 10.3 smm state-save area when the processor acknowledges an smi# interrupt by asserting smiact#, it saves its state in a 512-byte smm state-save area shown in table 41. the save begins at the top of the smm memory area (smm base address + ffffh) and fills down to smm base address + fe00h. table 41 shows the offsets in the smm state-save area relative to the smm base address. the smm service routine can alter any of the read/write values in the state-save area. table 41. smm state-save area map address offset contents saved fffch cr0 fff8h cr3 fff4h eflags fff0h eip ffech edi ffe8h esi ffe4h ebp ffe0h esp ffdch ebx ffd8h edx ffd4h ecx ffd0h eax ffcch dr6 ffc8h dr7 ffc4h tr ffc0h ldtr base ffbch gs ffb8h fs ffb4h ds ffb0h ss ffach cs ffa8h es notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 10 system management mode (smm) 217 ffa4h i/o trap dword ffa0h ff9ch i/o trap eip* ff98h ff94h ff90h idt base ff8ch idt limit ff88h gdt base ff84h gdt limit ff80h tss attr ff7ch tss base ff78h tss limit ff74h ff70h ldt high ff6ch ldt low ff68h gs attr ff64h gs base ff60h gs limit ff5ch fs attr ff58h fs base ff54h fs limit ff50h ds attr ff4ch ds base ff48h ds limit ff44h ss attr ff40h ss base ff3ch ss limit ff38h cs attr ff34h cs base ff30h cs limit ff2ch es attr table 41. smm state-save area map (continued) address offset contents saved notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle. 218 system management mode (smm) chapter 10 amd-k6 ? - iii processor data sheet 21918b/0october 1999 10.4 smm revision identifier the smm revision identifier at offset fefch in the smm state-save area specifies the version of smm and the extensions that are available on the processor. the smm revision identifier fields are as follows: n bits 31C18 reserved n bit 17 smm base address relocation (1 = enabled) n bit 16 i/o trap restart (1 = enabled) n bits 15C0 smm revision level for the AMD-K6-III processor = 0002h ff28h es base ff24h es limit ff20h ff1ch ff18h ff14h cr2 ff10h cr4 ff0ch i/o restart esi* ff08h i/o restart ecx* ff04h i/o restart edi* ff02h halt restart slot ff00h i/o trap restart slot fefch smm revid fef8h smm base fef7hCfe00h table 41. smm state-save area map (continued) address offset contents saved notes: no data dump at that address * only contains information if smi# is asserted during a valid i/o bus cycle. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 10 system management mode (smm) 219 table 42 shows the format of the smm revision identifier. 10.5 smm base address during reset, the processor sets the base address of the code-segment (cs) for the smm memory areathe smm base addressto its default, 0003_0000h. the smm base address at offset fef8h in the smm state-save area can be changed by the smm service routine to any address that is aligned to a 32-kbyte boundary. (locations not aligned to a 32-kbyte boundary cause the processor to enter the shutdown state when executing the rsm instruction.) in some operating environments it may be desirable to relocate the 64-kbyte smm memory area to a high memory area in order to provide more low memory for legacy software. during system initialization, the base of the 64-kbyte smm memory area is relocated by the bios. to relocate the smm base address, the system enters the smm handler at the default address. this handler changes the smm base address location in the smm state-save area, copies the smm handler to the new location, and exits smm. the next time smm is entered, the processor saves its state at the new base address. this new address is used for every smm entry until the smm base address in the smm state-save area is changed or a hardware reset occurs. 10.6 halt restart slot during entry into smm, the halt restart slot at offset ff02h in the smm state-save area indicates if smm was entered from the halt state. before returning from smm, the halt restart slot (offset ff02h) can be written to by the smm service routine to specify whether the return from smm takes the processor back to the halt state or to the next instruction after the hlt instruction. table 42. smm revision identifier 31C18 17 16 15C0 reserved smm base relocation i/o trap extension smm revision level 0 1 1 0002h 220 system management mode (smm) chapter 10 amd-k6 ? - iii processor data sheet 21918b/0october 1999 upon entry into smm, the halt restart slot is defined as follows: n bits 15C1 reserved n bit 0 point of entry to smm: 1 = entered from halt state 0 = not entered from halt state after entry into the smi handler and before returning from smm, the halt restart slot can be written using the following definition: n bits 15C1 reserved n bit 0 point of return when exiting from smm: 1 = return to halt state 0 = return to next instruction after the hlt instruction if the return from smm takes the processor back to the halt state, the hlt instruction is not re-executed, but the halt special bus cycle is driven on the bus after the return. 10.7 i/o trap dword if the assertion of smi# is recognized during the execution of an i/o instruction, the i/o trap dword at offset ffa4h in the smm state-save area contains information about the instruction. the fields of the i/o trap dword are configured as follows: n bits 31C16 i/o port address n bits 15C4 reserved n bit 3 rep (repeat) string operation (1 = rep string, 0 = not a rep string) n bit 2 i/o string operation (1 = i/o string, 0 = not an i/o string) n bit 1 valid i/o instruction (1 = valid, 0 = invalid) n bit 0 input or output instruction (1 = inx, 0 = outx) table 43 shows the format of the i/o trap dword. table 43. i/o trap dword configuration 3116 154 3 2 1 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 10 system management mode (smm) 221 the i/o trap dword is related to the i/o trap restart slot (see i/o trap restart slot). if bit 1 of the i/o trap dword is set by the processor, it means that smi# was asserted during the execution of an i/o instruction. the smi handler tests bit 1 to see if there is a valid i/o instruction trapped. if the i/o instruction is valid, the smi handler is required to ensure the i/o trap restart slot is set properly. the i/o trap restart slot informs the processor whether it should re-execute the i/o instruction after the rsm or execute the instruction following the trapped i/o instruction. note: if smi# is sampled asserted during an i/o bus cycle a minimum of three clock edges before brdy# is sampled asserted, the associated i/o instruction is guaranteed to be trapped by the smi handler. 10.8 i/o trap restart slot the i/o trap restart slot at offset ff00h in the smm state-save area specifies whether the trapped i/o instruction should be re-executed on return from smm. this slot in the state-save area is called the i/o instruction restart function. re-executing a trapped i/o instruction is useful, for example, if an i/o write occurs to a disk that is powered down. the system logic monitoring such an access can assert smi#. then the smm service routine would query the system logic, detect a failed i/o write, take action to power-up the i/o device, enable the i/o trap restart slot feature, and return from smm. the fields of the i/o trap restart slot are defined as follows: n bits 31C16 reserved n bits 15C0 i/o instruction restart on return from smm: 0000h = execute the next instruction after the trapped i/o instruction 00ffh = re-execute the trapped i/o instruction table 44 shows the format of the i/o trap restart slot. table 44. i/o trap restart slot 31C16 15C0 reserved i/o instruction restart on return from smm: n 0000h = execute the next instruction after the trapped i/o n 00ffh = re-execute the trapped i/o instruction 222 system management mode (smm) chapter 10 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the processor initializes the i/o trap restart slot to 0000h upon entry into smm. if smm was entered due to a trapped i/o instruction, the processor indicates the validity of the i/o instruction by setting or clearing bit 1 of the i/o trap dword at offset ffa4h in the smm state-save area. the smm service routine should test bit 1 of the i/o trap dword to determine if a valid i/o instruction was being executed when entering smm and before writing the i/o trap restart slot. if the i/o instruction is valid, the smm service routine can safely rewrite the i/o trap restart slot with the value 00ffh, which causes the processor to re-execute the trapped i/o instruction when the rsm instruction is executed. if the i/o instruction is invalid, writing the i/o trap restart slot has undefined results. if a second smi# is asserted and a valid i/o instruction was trapped by the first smm handler, the processor services the second smi# prior to re-executing the trapped i/o instruction. the second entry into smm never has bit 1 of the i/o trap dword set, and the second smm service routine must not rewrite the i/o trap restart slot. during a simultaneous smi# i/o instruction trap and debug breakpoint trap, the AMD-K6-III processor first responds to the smi# and postpones recognizing the debug exception until after returning from smm via the rsm instruction. if the debug registers dr3Cdr0 are used while in smm, they must be saved and restored by the smm handler. the processor automatically saves and restores dr7Cdr6. if the i/o trap restart slot in the smm state-save area contains the value 00ffh when the rsm instruction is executed, the debug trap does not occur until after the i/o instruction is re-executed. 10.9 exceptions, interrupts, and debug in smm during an smi# i/o trap, the exception/interrupt priority of the AMD-K6-III processor changes from its normal priority. the normal priority places the debug traps at a priority higher than the sampling of the flush# or smi# signals. however, during an smi# i/o trap, the sampling of the flush# or smi# signals takes precedence over debug traps. the processor recognizes the assertion of nmi within smm immediately after the completion of an iret instruction. once nmi is recognized within smm, nmi recognition remains enabled until smm is exited, at which point nmi masking is restored to the state it was in before entering smm. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 223 11 test and debug the AMD-K6-III processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. in addition, the debug features of the processor allow designers to debug the instruction execution of software components. this chapter describes the following test and debug features: n built-in self-test (bist) the bist, which is invoked after the falling transition of reset, runs internal tests that exercise most on-chip ram structures. n tri-state test mode a test mode that causes the processor to float its output and bidirectional pins. n boundary-scan test access port (tap) the joint test action group (jtag) test access function defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. n cache inhibit a feature that disables the processors internal l1 and l2 caches. n level-2 cache array access register (l2aar) the AMD-K6-III processor provides the l2aar that allows for direct access to the l2 cache and l2 tag arrays. n debug support consists of all x86-compatible software debug features, including the debug extensions. 11.1 built-in self-test (bist) following the falling transition of reset, the processor unconditionally runs its bist. the internal resources tested during bist include the following: n l1 instruction and data caches n l2 cache n instruction and data translation lookaside buffers (tlbs) the contents of the eax general-purpose register after the completion of reset indicate if the bist was successful. if eax contains 0000_0000h, then bist was successful. if eax is non-zero, the bist failed. following the completion of the bist, 224 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the processor jumps to address ffff_fff0h to start instruction execution, regardless of the outcome of the bist. the bist takes approximately 5,000,000 processor clocks to complete. 11.2 tri-state test mode the tri-state test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. in this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ate) to test components that drive the same signals as those the processor floats. if the flush# signal is sampled low during the falling transition of reset, the processor enters the tri-state test mode. (see flush# (cache flush) on page 103 for the specific sampling requirements.) the signals floated in the tri-state test mode are as follows: the vcc2det, vcc2h/l#, and tdo signals are the only outputs not floated in the tri-state test mode. vcc2det and vcc2h/l# must remain low to ensure the system continues to supply the specified processor core voltage to the v cc2 pins. tdo is never floated because the boundary-scan test access port must remain enabled at all times, including during the tri-state test mode. the tri-state test mode is exited when the processor samples reset asserted. n a[31:3] n d/c# n m/io# n ads# n d[63:0] n pcd n adsc# n dp[7:0] n pchk# n ap n ferr# n pwt n apchk# n hit# n scyc n be[7:0]# n hitm# n smiact# n breq n hlda n w/r# n cache# n lock# 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 225 11.3 boundary-scan test access port (tap) the boundary-scan test access port (tap) is an ieee standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. the AMD-K6-III processor supports the tap standard defined in the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. boundary scan testing uses a shift register consisting of the serial interconnection of boundary-scan cells that correspond to each i/o buffer of the processor. this non-inverting register chain, called a boundary scan register (bsr), can be used to capture the state of every processor pin and to drive every processor output and bidirectional pin to a known state. each bsr of every component on a board that implements the boundary-scan architecture can be serially interconnected to enable component interconnect testing. test access port the tap consists of the following: n test access port (tap) controller the tap controller is a synchronous, finite state machine that uses the tms and tdi input signals to control a sequence of test operations. see tap controller state machine on page 232 for a list of tap states and their definition. n instruction register (ir) the ir contains the instructions that select the test operation to be performed and the test data register (tdr) to be selected. see tap registers on page 226 for more details on the ir. n test data registers (tdr) the three tdrs are used to process the test data. each tdr is selected by an instruction in the instruction register (ir). see tap registers on page 226 for a list of these registers and their functions. tap signals the test signals associated with the tap controller are as follows: n tck the test clock for all tap operations. the rising edge of tck is used for sampling tap signals, and the falling edge of tck is used for asserting tap signals. the state of the tms signal sampled on the rising edge of tck causes 226 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the state transitions of the tap controller to occur. tck can be stopped in the logic 0 or 1 state. n tdi the test data input represents the input to the most significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit into their respective registers on the rising edge of tck. n tdo the test data output represents the output of the least significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit out of their respective registers on the falling edge of tck. n tms the test mode select input specifies the test function and sequence of state changes for boundary-scan testing. if tms is sampled high for five or more consecutive clocks, the tap controller enters its reset state. n trst# the test reset signal is an asynchronous reset that unconditionally causes the tap controller to enter its reset state. refer to electrical data on page 259 and signal switching characteristics on page 267 to obtain the electrical specifications of the test signals. tap registers the AMD-K6-III processor provides an instruction register (ir) and three test data registers (tdr) to support the boundary-scan architecture. the ir and one of the tdrsthe boundary-scan register (bsr)consist of a shift register and an output register. the shift register is loaded in parallel in the capture states. (see tap controller state machine on page 232 for a description of the tap controller states.) in addition, the shift register is loaded and shifted serially in the shift states. the output register is loaded in parallel from its corresponding shift register in the update states. instruction register (ir). the ir is a 5-bit register, without parity, that determines which instruction to run and which test data register to select. when the tap controller enters the capture-ir state, the processor loads the following bits into the ir shift register: n 01b loaded into the two least significant bits, as specified by the ieee 1149.1 standard n 000b loaded into the three most significant bits 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 227 loading 00001b into the ir shift register during the capture-ir state results in loading the sample/preload instruction. for each entry into the shift-ir state, the ir shift register is serially shifted by one bit toward the tdo pin. during the shift, the most significant bit of the ir shift register is loaded from the tdi pin. the ir output register is loaded from the ir shift register in the update-ir state, and the current instruction is defined by the ir output register. see tap instructions on page 231 for a list and definition of the instructions supported by the AMD-K6-III processor. boundary scan register (bsr). the bsr is a test data register consisting of the interconnection of 152 boundary-scan cells. each output and bidirectional pin of the processor requires a two-bit cell, where one bit corresponds to the pin and the other bit is the output enable for the pin. when a 0 is shifted into the enable bit of a cell, the corresponding pin is floated, and when a 1 is shifted into the enable bit, the pin is driven valid. each input pin requires a one-bit cell that corresponds to the pin. the last cell of the bsr is reserved and does not correspond to any processor pin. the total number of bits that comprise the bsr is 281. table 45 on page 229 lists the order of these bits, where tdi is the input to bit 280, and tdo is driven from the output of bit 0. the entries listed as pin _e (where pin is an output or bidirectional signal) are the enable bits. if the bsr is the register selected by the current instruction and the tap controller is in the capture-dr state, the processor loads the bsr shift register as follows: n if the current instruction is sample/preload, then the current state of each input, output, and bidirectional pin is loaded. a bidirectional pin is treated as an output if its enable bit equals 1, and it is treated as an input if its enable bit equals 0. n if the current instruction is extest, then the current state of each input pin is loaded. a bidirectional pin is treated as an input, regardless of the state of its enable. 228 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 while in the shift-dr state, the bsr shift register is serially shifted toward the tdo pin. during the shift, bit 280 of the bsr is loaded from the tdi pin. the bsr output register is loaded with the contents of the bsr shift register in the update-dr state. if the current instruction is extest, the processors output pins, as well as those bidirectional pins that are enabled as outputs, are driven with their corresponding values from the bsr output register. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 229 table 45. boundary scan bit definitions bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable 280 d35_e 247 d19 214 bf1 181 a24 148 a14 115 be7# 279 d35 246 d16_e 213 bf2 180 a18_e 147 a17_e 114 pcd_e 278 d29_e 245 d16 212 r eset 179 a18 146 a17 113 pcd 277 d29 244 d17_e 211 bf0 178 a5_e 145 a16_e 112 dc_e 276 d33_e 243 d17 210 flush# 177 a5 144 a16 111 d/c# 275 d33 242 d15_e 209 intr 176 eads# 143 hit_e 110 wr_e 274 d27_e 241 d15 208 nmi 175 a22_e 142 hit# 109 w/r# 273 d27 240 dp1_e 207 smi# 174 a22 141 ads_e 108 na# 272 dp0_e 239 dp1 206 a25_e 173 ahold 140 ads# 107 pwt_e 271 dp0 238 d13_e 205 a25 172 hitm_e 139 clk 106 pwt 270 dp3_e 237 d13 204 a26_e 171 hitm# 138 adsc_e 105 cache_e 269 dp3 236 d6_e 203 a26 170 a4_e 137 adsc# 104 cache# 268 d25_e 235 d6 202 a29_e 169 a4 136 be0_e 103 wb/wt# 267 d25 234 d14_e 201 a29 168 a9_e 135 be0# 102 mio_e 266 d0_e 233 d14 200 a28_e 167 a9 134 ap_e 101 m/io# 265 d0 232 d11_e 199 a28 166 a8_e 133 ap 100 breq_e 264 d30_e 231 d11 198 a23_e 165 a8 132 be1_e 99 breq 263 d30 230 d1_e 197 a23 164 a19_e 131 be1# 98 scyc_e 262 dp2_e 229 d1 196 a27_e 163 a19 130 be2_e 97 scyc 261 dp2 228 d12_e 195 a27 162 boff# 129 be2# 96 lock_e 260 d2_e 227 d12 194 a11_e 161 a6_e 128 brdy# 95 lock# 259 d2 226 d10_e 193 a11 160 a6 127 be3_e 94 apchk_e 258 d28_e 225 d10 192 a3_e 159 a20_e 126 be3# 93 apchk# 257 d28 224 d7_e 191 a3 158 a20 125 be4_e 92 pchk_e 256 d24_e 223 d7 190 a31_e 157 a13_e 124 be4# 91 pchk# 255 d24 222 d8_e 189 a31 156 a13 123 br dyc# 90 ewbe# 254 d26_e 221 d8 188 a21_e 155 a12_e 122 be5_e 89 smiact_e 253 d26 220 d9_e 187 a21 154 a12 121 be5# 88 smiact# 252 d21_e 219 d9 186 a30_e 153 a10_e 120 be6_e 87 fer r_e 251 d21 218 hold 185 a30 152 a10 119 be6# 86 fer r# 250 d18_e 217 stpclk# 184 a7_e 151 a15_e 118 ken# 85 d20_e 249 d18 216 init 183 a7 150 a15 117 inv 84 d20 248 d19_e 215 ignne# 182 a24_e 149 a14_e 116 be7_e 83 d22_e 230 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 device identification register (dir). the dir is a 32-bit test data register selected during the execution of the idcode instruction. the fields of the dir and their values are shown in table 46 and are defined as follows: n version code this 4-bit field is incremented by amd manufacturing for each major revision of silicon. n part number this 16-bit field identifies the specific processor model. n manufacturer this 11-bit field identifies the manufacturer of the component (amd). n lsb the least significant bit (lsb) of the dir is always set to 1, as specified by the ieee 1149.1 standard. 82 d22 68 d54_e 54 d47_e 40 d62_e 26 d38_e 12 d3_e 81 d23_e 67 d54 53 d47 39 d62 25 d38 11 d3 80 d23 66 d50_e 52 d59_e 38 d49_e 24 d58_e 10 d39_e 79 a20m# 65 d50 51 d59 37 d49 23 d58 9 d39 78 hlda_e 64 d56_e 50 d51_e 36 dp4_e 22 d42_e 8 d32_e 77 hlda 63 d56 49 d51 35 dp4 21 d42 7 d32 76 dp7_e 62 d55_e 48 d45_e 34 d4_e 20 d36_e 6 d5_e 75 dp7 61 d55 47 d45 33 d4 19 d36 5 d5 74 d63_e 60 d48_e 46 d61_e 32 d46_e 18 d60_e 4 d37_e 73 d63 59 d48 45 d61 31 d46 17 d60 3 d37 72 d52_e 58 d57_e 44 dp5_e 30 d41_e 16 d40_e 2 d31_e 71 d52 57 d57 43 dp5 29 d41 15 d40 1 d31 70 dp6_e 56 d53_e 42 d43_e 28 d44_e 14 d34_e 0 reserved 69dp655d5341d4327d4413d34 table 45. boundary scan bit definitions (continued) bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable table 46. device identification register version code (bits 31C28) part number (bits 27C12) manufacturer (bits 11C1) lsb (bit 0) xh 0590h 00000000001b 1b 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 231 bypass register (br). the br is a test data register consisting of a 1-bit shift register that provides the shortest path between tdi and tdo. when the processor is not involved in a test operation, the br can be selected by an instruction to allow the transfer of test data through the processor without having to serially scan the test data through the bsr. this functionality preserves the state of the bsr and significantly reduces test time. the br register is selected by the bypass and highz instructions as well as by any instructions not supported by the AMD-K6-III processor. tap instructions the processor supports the three instructions required by the ieee 1149.1 standardextest, sample/preload, and bypassas well as two additional optional instructions idcode and highz. table 47 shows the complete set of tap instructions supported by the processor along with the 5-bit instruction register encoding and the register selected by each instruction. extest. when the extest instruction is executed, the processor loads the bsr shift register with the current state of the input and bidirectional pins in the capture-dr state and drives the output and bidirectional pins with the corresponding values from the bsr output register in the update-dr state. table 47. supported tap instructions instruction encoding register description extest 1 00000b bsr sample inputs and drive outputs sample / preload 00001b bsr sample inputs and outputs, then load the bsr idcode 00010b dir read dir highz 00011b br float outputs and bidirectional pins bypass 2 00100bC11110b br undefined instruction, execute the bypass instruction bypass 3 11111b br connect tdi to tdo to bypass the bsr notes: 1. following the execution of the extest instruction, the processor must be reset in order to return to normal, non-test operati on. 2. these instruction encodings are undefined on the amd-k6- iii processor and default to the bypass instruction. 3. because the tdi input contains an internal pullup, the bypass instruction is executed if the tdi input is not connected or op en during an instruction scan operation. the bypass instruction does not affect the normal operational state of the processor. 232 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 sample/preload. the sample/preload instruction performs two functions. these functions are as follows: n during the capture-dr state, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. n during the update-dr state, the bsr output register is loaded from the bsr shift register in preparation for the next extest instruction. the sample/preload instruction does not affect the normal operational state of the processor. bypass. the bypass instruction selects the br register, which reduces the boundary-scan length through the processor from 281 to one (tdi to br to tdo). the bypass instruction does not affect the normal operational state of the processor. idcode. the idcode instruction selects the dir register, allowing the device identification code to be shifted out of the processor. this instruction is loaded into the ir when the tap controller is reset. the idcode instruction does not affect the normal operational state of the processor. highz. the highz instruction forces all output and bidirectional pins to be floated. during this instruction, the br is selected and the normal operational state of the processor is not affected. tap controller state machine the tap controller state diagram is shown in figure 86 on page 233. state transitions occur on the rising edge of tck. the logic 0 or 1 next to the states represents the value of the tms signal sampled by the processor on the rising edge of tck. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 233 figure 86. tap state diagram test-logic-reset shift-dr pause-dr update-dr update-ir 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 run-test/idle exit2-ir exit1-ir pause-ir shift-ir select-dr-scan select-ir-scan capture-dr capture-ir exit1-dr exit2-dr ieee std 1149.1-1990, copyright ? 1990. ieee. all rights reserved 234 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the states of the tap controller are described as follows: test-logic-reset. this state represents the initial reset state of the tap controller and is entered when the processor samples reset asserted, when trst# is asynchronously asserted, and when tms is sampled high for five or more consecutive clocks. in addition, this state can be entered from the select-ir-scan state. the ir is initialized with the idcode instruction, and the processors normal operation is not affected in this state. capture-dr. during the sample/preload instruction, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. during the extest instruction, the processor loads the bsr shift register with the current state of every input and bidirectional pin. capture-ir. when the tap controller enters the capture-ir state, the processor loads 01b into the two least significant bits of the ir shift register and loads 000b into the three most significant bits of the ir shift register. shift-dr. while in the shift-dr state, the selected tdr shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the tdr is loaded from the tdi pin. shift-ir. while in the shift-ir state, the ir shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the ir is loaded from the tdi pin. update-dr. during the sample/preload instruction, the bsr output register is loaded with the contents of the bsr shift register. during the extest instruction, the output pins, as well as those bidirectional pins defined as outputs, are driven with their corresponding values from the bsr output register. update-ir. in this state, the ir output register is loaded from the ir shift register, and the current instruction is defined by the ir output register. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 235 the following states have no effect on the normal or test operation of the processor other than as shown in figure 86 on page 233: n run-test/idlethis state is an idle state between scan operations. n select-dr-scanthis is the initial state of the test data register state transitions. n select-ir-scanthis is the initial state of the instruction register state transitions. n exit1-drthis state is entered to terminate the shifting process and enter the update-dr state. n exit1-irthis state is entered to terminate the shifting process and enter the update-ir state. n pause-drthis state is entered to temporarily stop the shifting process of a test data register. n pause-irthis state is entered to temporarily stop the shifting process of the instruction register. n exit2-drthis state is entered in order to either terminate the shifting process and enter the update-dr state or to resume shifting following the exit from the pause-dr state. n exit2-irthis state is entered in order to either terminate the shifting process and enter the update-ir state or to resume shifting following the exit from the pause-ir state. 11.4 cache inhibit purpose the AMD-K6-III processor provides a means for inhibiting the normal operation of its internal l1 and l2 caches while still supporting an external cache. this capability allows system designers to disable the l1 and l2 caches during the testing and debug of a l3 cache. if the cache inhibit bit (bit 3) of test register 12 (tr12) is set to 0, the processors l1 and l2 caches are enabled and operate as described in cache organization on page 179. if the cache inhibit bit is set to 1, the l1 and l2 caches are disabled and no new cache lines are allocated. even though new allocations do not occur, valid l1 and l2 cache lines remain valid and are read by the processor when a requested address hits a cache line. in addition, the processor continues to support inquire cycles 236 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 initiated by the system logic, including the execution of writeback cycles when a modified cache line is hit. while the l1 and l2 are inhibited, the processor continues to drive the pcd output signal appropriately, which system logic can use to control external l3 caching. in order to completely disable the l1 and l2 caches so no valid lines exist in the cache, the cache inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: n asserting the flush# input signal n executing the wbinvd instruction n executing the invd instruction (modified cache lines are not written back to memory) n make use of the page flush/invalidate register (pfir) (see pfir on page 198) 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 237 11.5 l2 cache and tag array testing level-2 cache array access register (l2aar) the AMD-K6-III processor provides the level-2 cache array access register (l2aar) that allows for direct access to the l2 cache and l2 tag arrays. the 256-kbyte l2 cache in the AMD-K6-III is organized as shown in figure 87: n four 64-kbyte ways n each way contains 1024 sectors n each set contains four 64-byte sectors (one sector in each way) n each sector contains two 32-byte cache lines n each cache line contains four 8-byte octets n each octet contains an upper and lower dword (4 bytes) each line within a sector contains its own mesi state bits, and associated with each sector is a tag and lru (least recently used) information. figure 87. l2 cache organization figure 88 shows the l2 cache sector and line organization. if bit 5 of the address of a cache line equals 1, then this cache line is stored in line 1 of a sector. similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in line 0 of a sector. 1024 sets set 0 64 bytes way 2 line1/mesi line0/mesi tag/lru 64 bytes way 1 line1/mesi line0/mesi tag/lru 64 bytes way 0 line1/mesi line0/mesi tag/lru 64 bytes way 3 line1/mesi line0/mesi tag/lru set 1023 238 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 88. l2 cache sector and line organization the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 89). bit 20 of edx (t/d) determines whether the access is to the l2 cache data or tag. table 48 describes the operation that is performed based on the instruction and the t/d bit. figure 89. l2 tag or data location - edx upper dword lower dword octet 0 line 1 octet 1 octet 2 octet 3 upper dword lower dword line 0 sector reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 239 when the l2aar is read or written, edx is left unchanged. this facilitates multiple accesses when testing the entire cache/tag array. if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format as illustrated in figure 90. similarly, if the l2 cache data is written, the write data is taken from eax. figure 90. l2 data - eax if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 91. similarly, if the l2 tag is written, the write data is taken from eax. when writing to the l2 tag, special consideration must be given to the least significant bit of the tag field of the eax register eax[15]. the length of the l2 tag required to support the 256-kbyte l2 cache on the AMD-K6-III processor is 16 bits, which corresponds to bits 31:16 of the eax register. however, the processor provides a total of 17 bits for storing the l2 tag that is, 16 bits for the tag (eax[31:16]), plus an additional bit table 48. tag versus data selector instruction t/d (edx[20]) operation rdmsr 0 read dword from l2 data array into eax. dword location is specified by edx. rdmsr 1 read tag, line state and lru information from l2 tag array into eax. location of tag is specified by edx. wrmsr 0 write dword to the l2 data array using data in eax. dword location is specified by edx. wrmsr 1 write tag, line state and lru information into l2 tag array from eax. location of tag is specified by edx. 0 31 data 240 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 for internal purposes (eax[15]). during normal operation, the processor ensures that this additional bit (bit 15) always corresponds to the set in which the tag resides. note that bits 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. in order to set the full 17-bit l2 tag properly when using the l2aar register, eax[15] must likewise correspond to the set in which the tag is being writtenthat is, eax[15] must be equal to edx[15] (refer to figure 89 and figure 91). it is important to note that this special consideration is required if the processor will subsequently be expected to properly execute instructions or access data from the l2 cache following the setup of the l2 cache by means of the l2aar register. if the intent of using the l2aar register is solely to test or debug the l2 cache without the subsequent intent of executing instructions or accessing data from the l2 cache, then this consideration is not required. when accessing the l2 tag, the line, octet, and dword fields of the edx register are ignored. figure 91. l2 tag information - eax lru (least recently used). for the 4-way set associative l2 cache, each way has a 2-bit lru field for each sector. values for the lru field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is most recently used, and 11b indicates that the sector is least recently used (see figure 92). eax[7:6] indicate lru information for way 0, eax[5:4] for way 1, eax[3:2] for way 2, and eax[1:0] for way 3. c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 241 figure 92. lru byte 11.6 debug the AMD-K6-III processor implements the standard x86 debug functions, registers, and exceptions. in addition, the processor supports the i/o breakpoint debug extension. the debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. the exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. the following sections describe the debug registers and the various types of breakpoints and exceptions that the processor supports. debug registers figures 93 through 96 show the 32-bit debug registers supported by the processor. 7654 32 1 0 way 2 lru values 00b most recently used 01b used more recent than 10b, but less recent than 00b 10b used more recent than 11b, but less recent than 01b 11b least recently used way 3 way 0 way 1 242 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 93. debug register dr7 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 g 0 g 1 l 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 reserved symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16 symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 243 figure 94. debug register dr6 figure 95. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 b t b d b 3 reserved symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4 244 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 96. debug registers dr3, dr2, dr1, and dr0 dr3Cdr0. the processor allows the setting of up to four breakpoints. dr3Cdr0 contain the linear addresses for breakpoint 3 through breakpoint 0, respectively, and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. debug register dr7 defines the specific type of cycle that must occur in order for the breakpoint to occur. dr5Cdr4. when debugging extensions are disabled (bit 3 of cr4 is set to 0), the dr5 and dr4 registers are mapped to dr7 and dr6, respectively, in order to be software compatible with previous generations of x86 processors. when debugging 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 245 extensions are enabled (bit 3 of cr4 is set to 1), any attempt to load dr5 or dr4 results in an undefined opcode exception. likewise, any attempt to store dr5 or dr4 also results in an undefined opcode exception. dr6. if a breakpoint is enabled in dr7, and the breakpoint conditions as defined in dr7 occur, then the corresponding b-bit (b3Cb0) in dr6 is set to 1. in addition, any other breakpoints defined using these particular breakpoint conditions are reported by the processor by setting the appropriate b-bits in dr6, regardless of whether these breakpoints are enabled or disabled. however, if a breakpoint is not enabled, a debug exception does not occur for that breakpoint. if the processor decodes an instruction that writes or reads dr7 through dr0, the bd bit (bit 13) in dr6 is set to 1 (if enabled in dr7) and the processor generates a debug exception. this operation allows control to pass to the debugger prior to debug register access by software. if the trap flag (bit 8) of the eflags register is set to 1, the processor generates a debug exception after the successful execution of every instruction (single-step operation) and sets the bs bit (bit 14) in dr6 to indicate the source of the exception. when the processor switches to a new task and the debug trap bit (t-bit) in the corresponding task state segment (tss) is set to 1, the processor sets the bt bit (bit 15) in dr6 and generates a debug exception. dr7. when set to 1, l3Cl0 locally enable breakpoints 3 through 0, respectively. l3Cl0 are set to 0 whenever the processor executes a task switch. setting l3Cl0 to 0 disables the breakpoints and ensures that these particular debug exceptions are only generated for a specific task. when set to 1, g3Cg0 globally enable breakpoints 3 through 0, respectively. unlike l3Cl0, g3Cg0 are not set to 0 whenever the processor executes a task switch. not setting g3Cg0 to 0 allows breakpoints to remain enabled across all tasks. if a breakpoint is enabled globally but disabled locally, the global enable overrides the local enable. 246 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 the le (bit 8) and ge (bit 9) bits in dr7 have no effect on the operation of the processor and are provided in order to be software compatible with previous generations of x86 processors. when set to 1, the gd bit in dr7 (bit 13) enables the debug exception associated with the bd bit (bit 13) in dr6. this bit is set to 0 when a debug exception is generated. len3Clen0 and rw3Crw0 are two-bit fields in dr7 that specify the length and type of each breakpoint as defined in table 49. debug exceptions a debug exception is categorized as either a debug trap or a debug fault. a debug trap calls the debugger following the execution of the instruction that caused the trap. a debug fault calls the debugger prior to the execution of the instruction that caused the fault. all debug traps and faults generate either an interrupt 01h or an interrupt 03h exception. table 49. dr7 len and rw definitions len bits 1 rw bits breakpoint 00b 00b 2 instruction execution 00b 01b one-byte data write 01b two-byte data write 11b four-byte data write 00b 10b 3 one-byte i/o read or write 01b two-byte i/o read or write 11b four-byte i/o read or write 00b 11b one-byte data read or write 01b two-byte data read or write 11b four-byte data read or write notes: 1. len bits equal to 10b is undefined. 2. when rw equals 00b, len must be equal to 00b. 3. when rw equals 10b, debugging extensions (de) must be enabled (bit 3 of cr4 must be set to 1). if de is set to 0, then rw equal to 10b is undefined. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 11 test and debug 247 interrupt 01h. the following events are considered debug traps that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for data and i/o cycles n single step trap n ta sk sw itch trap the following events are considered debug faults that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for instruction execution n bd bit in dr6 set to 1 interrupt 03h. the int 3 instruction is defined in the x86 architecture as a breakpoint instruction. this instruction causes the processor to generate an interrupt 03h exception. this exception is a debug trap because the debugger is called following the execution of the int 3 instruction. the int 3 instruction is a one-byte instruction (opcode cch) typically used to insert a breakpoint in software by writing cch to the address of the first byte of the instruction to be trapped (the target instruction). following the trap, if the target instruction is to be executed, the debugger must replace the int 3 instruction with the first byte of the target instruction. 248 test and debug chapter 11 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 12 clock control 249 12 clock control the AMD-K6-III processor supports five modes of clock control. the processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (see power dissipation on page 262 for the maximum power dissipation of the AMD-K6-III processor within the normal and reduced-power states.) the five clock-control states supported are as follows: n normal state : the processor is running in real mode, virtual-8086 mode, protected mode, or system management mode (smm). in this state, all clocks are runningincluding the external bus clock clk and the internal processor clockand the full features and functions of the processor are available. n halt state : this low-power state is entered following the successful execution of the hlt instruction. during this state, the internal processor clock is stopped. n stop grant state : this low-power state is entered following the recognition of the assertion of the stpclk# signal. during this state, the internal processor clock is stopped. n stop grant inquire state : this state is entered from the halt state and the stop grant state as the result of a system-initiated inquire cycle. n stop clock state : this low-power state is entered from the stop grant state when the clk signal is stopped. the following sections describe each of the four low-power states. figure 97 on page 254 illustrates the clock control state transitions. 250 clock control chapter 12 amd-k6 ? - iii processor data sheet 21918b/0october 1999 12.1 halt state enter halt state during the execution of the hlt instruction, the AMD-K6-III processor executes a halt special cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted (if not masked off), the processor enters the halt state in which the processor disables most of its internal clock distribution. in order to support the following operations, the internal phase-lock loop (pll) still runs, and some internal resources are still clocked in the halt state: n inquire cycles: the processor continues to sample ahold, boff#, and hold in order to support inquire cycles that are initiated by the system logic. the processor transitions to the stop grant inquire state during the inquire cycle. after returning to the halt state following the inquire cycle, the processor does not execute another halt special cycle. n flush cycles: the processor continues to sample flush#. if flush# is sampled asserted, the processor performs the flush operation in the same manner as it is performed in the normal state. upon completing the flush operation, the processor executes the halt special cycle which indicates the processor is in the halt state. n time stamp counter (tsc): the tsc continues to count in the halt state. n signal sampling: the processor continues to sample init, intr, nmi, reset, and smi#. after entering the halt state, all signals driven by the processor retain their state as they existed following the completion of the halt special cycle. exit halt state the AMD-K6-III processor remains in the halt state until it samples init, intr (if interrupts are enabled), nmi, reset, or smi# asserted. if any of these signals is sampled asserted, the processor returns to the normal state and performs the corresponding operation. all of the normal requirements for recognition of these input signals apply within the halt state. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 12 clock control 251 12.2 stop grant state enter stop grant state after recognizing the assertion of stpclk#, the AMD-K6-III processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and acknowledges the stpclk# assertion by executing a stop grant special bus cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted (if not masked off), the processor enters the stop grant state. the stop grant state is like the halt state in that the processor disables most of its internal clock distribution in the stop grant state. in order to support the following operations, the internal pll still runs, and some internal resources are still clocked in the stop grant state: n inquire cycles: the processor transitions to the stop grant inquire state during an inquire cycle. after returning to the stop grant state following the inquire cycle, the processor does not execute another stop grant special cycle. n time stamp counter (tsc): the tsc continues to count in the stop grant state. n signal sampling: the processor continues to sample init, intr, nmi, reset, and smi#. flush# is not recognized in the stop grant state (unlike while in the halt state). upon entering the stop grant state, all signals driven by the processor retain their state as they existed following the completion of the stop grant special cycle. exit stop grant state the AMD-K6-III processor remains in the stop grant state until it samples stpclk# negated or reset asserted. if stpclk# is sampled negated, the processor returns to the normal state in less than 10 bus clock (clk) periods. after the transition to the normal state, the processor resumes execution at the instruction boundary on which stpclk# was initially recognized. if stpclk# is recognized as negated in the stop grant state and subsequently sampled asserted prior to returning to the normal state, the AMD-K6-III processor guarantees that a minimum of one instruction is executed prior to re-entering the stop grant state. 252 clock control chapter 12 amd-k6 ? - iii processor data sheet 21918b/0october 1999 if init, intr (if interrupts are enabled), flush#, nmi, or smi# are sampled asserted in the stop grant state, the processor latches the edge-sensitive signals (init, flush#, nmi, and smi#), but otherwise does not exit the stop grant state to service the interrupt. when the processor returns to the normal state due to sampling stpclk# negated, any pending interrupts are recognized after returning to the normal state. to ensure their recognition, all of the normal requirements for these input signals apply within the stop grant state. if reset is sampled asserted in the stop grant state, the processor immediately returns to the normal state and the reset process begins. 12.3 stop grant inquire state enter stop grant inquire state the stop grant inquire state is entered from the stop grant state or the halt state when eads# is sampled asserted during an inquire cycle initiated by the system logic. the AMD-K6-III processor responds to an inquire cycle in the same manner as in the normal state by driving hit# and hitm#. if the inquire cycle hits a modified cache line, the processor performs a writeback cycle. exit stop grant inquire state following the completion of any writeback, the processor returns to the state from which it entered the stop grant inquire state. 12.4 stop clock state enter stop clock state if the clk signal is stopped while the AMD-K6-III processor is in the stop grant state, the processor enters the stop clock state. because all internal clocks and the pll are not running in the stop clock state, the stop clock state represents the minimum-power state of all clock control states. the clk signal must be held low while it is stopped. the stop clock state cannot be entered from the halt state. intr is the only input signal that is allowed to change states while the processor is in the stop clock state. however, intr is not sampled until the processor returns to the stop grant state. all other input signals must remain unchanged in the stop clock state. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 12 clock control 253 exit stop clock state the AMD-K6-III processor returns to the stop grant state from the stop clock state after the clk signal is started and the internal pll has stabilized. pll stabilization is achieved after the clk signal has been running within its specification for a minimum of 1.0 ms. the frequency of clk when exiting the stop clock state can be different than the frequency of clk when entering the stop clock state. the state of the bf[2:0] signals when exiting the stop clock state is ignored because the bf[2:0] signals are only sampled during the falling transition of reset. 254 clock control chapter 12 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 97. clock control state transitions eads# asserted eads# asserted hlt instruction stop grant state normal mode - real - virtual-8086 - protected - smm halt state stop clock state reset, smi#, init, or intr asserted stop grant inquire state stpclk# asserted stpclk# negated, or reset asserted clk started clk stopped writeback completed writeback completed 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 13 power and grounding 255 13 power and grounding 13.1 power connections the AMD-K6-III processor is a dual voltage device. two separate supply voltages are required: v cc2 and v cc3 . v cc2 provides the core voltage for the processor and v cc3 provides the i/o voltage. see electrical data on page 259 for the value and range of v cc2 and v cc3 . there are 28 v cc2 , 32 v cc3 , and 68 v ss pins on the AMD-K6-III processor. (see pin designations on page 295 for all power and ground pin designations.) the large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. for proper operation and functionality, all v cc2 , v cc3 , and v ss pins must be connected to the appropriate planes in the circuit board. the power planes have been arranged in a pattern to simplify routing and minimize crosstalk on the circuit board. the isolation region between two voltage planes must be at least 0.254mm if they are in the same layer of the circuit board. (see figure 98 on page 256.) in order to maintain a low-impedance current sink and reference, the ground plane must never be split. although the AMD-K6-III processor has two separate supply voltages, there are no special power sequencing requirements. the best procedure is to minimize the time between which v cc2 and v cc3 are either both on or both off. 256 power and grounding chapter 13 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 98. suggested component placement 13.2 decoupling recommendations in addition to the isolation region mentioned in power connections on page 255, adequate decoupling capacitance is required between the two system power planes and the ground plane to minimize ringing and to provide a low-impedance path for return currents. suggested decoupling capacitor placement is shown in figure 98. surface mounted capacitors should be used under the processors zif socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. for information and recommendations about the specific value, quantity, and location of the capacitors, see the amd-k6 ? processor power supply design application note , order# 21103. 0.254mm (min.) for isolation region v cc2 (core) plane v cc3 (i/o) plane c1 cc5 cc3 c2 + + + + c5 c6 c7 c11 c12 c13 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c29 c30 c31 cc4 + cc6 cc10 cc1 cc2 cc9 cc8 cc7 c8 c9 c10 c14 c15 c16 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 13 power and grounding 257 13.3 pin connection requirements for proper operation, the following requirements for signal pin connections must be met: n do not drive address and data signals into large capacitive loads at high frequencies. if necessary, use buffer chips to drive large capacitive loads. n leave all nc (no-connect) pins unconnected. n unused inputs should always be connected to an appropriate signal level. ? active low inputs that are not being used should be connected to v cc3 through a 20-kohm pullup resistor. ? active high inputs that are not being used should be connected to gnd through a pulldown resistor. n reserved signals can be treated in one of the following ways: ? as no-connect (nc) pins, in which case these pins are left unconnected ? as pins connected to the system logic as defined by the industry-standard super7 and socket 7 interface ? any combination of nc and socket 7 pins n keep trace lengths to a minimum. 258 power and grounding chapter 13 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 14 electrical data 259 14 electrical data 14.1 operating ranges the AMD-K6-III processor is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in table 50. table 50. operating ranges parameter minimum typical maximum comments v cc2 2.1 v 2.2 v 2.3 v note 1,2 2.3 v 2.4 v 2.5 v note 1,3 v cc3 3.135 v 3.3 v 3.6 v note 1 t case 0 c 70 cnote 4 65 cnote 5 notes: 1. v cc2 and v cc3 are referenced from v ss . 2. v cc2 specification for 2.2v component (opn suffixes afr and afx). 3. v cc2 specification for 2.4v component (opn suffix ahx). 4. case temperature range required for amd-k6- iii /xxxafr valid ordering part number combinations, where xxx represents the processor core frequency. 5. case temperature range required for amd-k6- iii /xxxafx and amd-k6- iii /xxxahx valid ordering part number combinations, where xxx represents the processor core frequency. 260 electrical data chapter 14 amd-k6 ? - iii processor data sheet 21918b/0october 1999 14.2 absolute ratings the AMD-K6-III processor is not designed to be operated beyond the operating ranges listed in table 50. exposure to conditions outside these operating ranges for extended periods of time can affect long-term reliability. permanent damage can occur if the absolute ratings listed in table 51 are exceeded. table 51. absolute ratings parameter minimum maximum comments v cc2 C0.5 v 2.4 v note 1 C0.5 v 2.6 v note 2 v cc3 C0.5 v 3.6 v v pin C0.5 v v cc3 + 0.5 v and 4.0 v note 3 t case (under bias) C65 c +110 c t storage C65 c +150 c notes: 1. v cc2 specification for 2.2v component (opn suffixes afr and afx). 2. v cc2 specification for 2.4 v component (opn suffix ahx). 3. v pin (the voltage on any i/o pin) must not be greater than 0.5 v above the voltage being applied to v cc3 . in addition, the v pin voltage must never exceed 4.0 v. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 14 electrical data 261 14.3 dc characteristics the dc characteristics of the AMD-K6-III processor are shown in table 52. table 52. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage C0.3 v +0.8 v v ih input high voltage 2.0 v v cc3 +0.3v note 1 v ol output low voltage 0.4 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 3.0-ma load i cc2 2.2 v power supply current 10.80 a 400 mhz, note 2, 9 12.15 a 450 mhz, note 2, 8 2.4 v power supply current 12.40 a 400 mhz, note 3, 9 13.50 a 450 mhz, note 3, 8 i cc3 3.3 v power supply current 0.62 a 400 mhz, note 4, 9 0.66 a 450 mhz, note 4, 8 i li input leakage current 15 m anote 5 i lo output leakage current 15 m anote 5 i il input leakage current bias with pullup C400 m anote 6 i ih input leakage current bias with pulldown 200 m anote 7 c in input capacitance 10 pf c out output capacitance 15 pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst#) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v cc3 refers to the voltage being applied to v cc3 during functional operation. 2. v cc2 = 2.3 v the maximum power supply current must be taken into account when designing a power supply. 3. v cc2 = 2.5 v the maximum power supply current must be taken into account when designing a power supply. 4. v cc3 = 3.6 v the maximum power supply current must be taken into account when designing a power supply. 5. refers to inputs and i/o without an internal pullup resistor and 0 v in v cc3. 6. refers to inputs with an internal pullup and v il = 0.4 v. 7. refers to inputs with an internal pulldown and v ih = 2.4 v. 8. clk frequency equals 100 mhz. 9. this specification applies to components using a clk frequency of 66 mhz or 100 mhz. 262 electrical data chapter 14 amd-k6 ? - iii processor data sheet 21918b/0october 1999 14.4 power dissipation table 53 contains the typical and maximum power dissipation of the AMD-K6-III processor during normal and reduced power states. table 53. typical and maximum power dissipation clock control state 2.2 v component 2.4 v component comments 400 mhz 7 450 mhz 6 400 mhz 7 450 mhz 6 normal (maximum thermal power) 18.10 w 20.20 w 26.80 w 29.50 w note 1, 2 normal (typical thermal power) 10.85 w 12.15 w 16.10 w 17.70 w note 3 stop grant / halt (maximum) 4.40 w 4.44 w 5.30 w 5.34 w note 4 stop clock (maximum) 4.00 w 4.00 w 4.80 w 4.80 w note 5 notes: 1. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal dissipation for the amd-k6- iii processor. 2. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with v cc2 = 2.2 v (for 2.2 v components) or v cc2 = 2.4 v (for 2.4 v components) and v cc3 = 3.3 v. 3. typical power is determined for the typical instruction sequences or functions associated with normal system operation with v cc2 = 2.2 v (for 2.2 v components) or v cc2 = 2.4 v (for 2.4 v components) and v cc3 = 3.3 v. 4. the clk signal and the internal pll are still running but most internal clocking has stopped. 5. the clk signal, the internal pll, and all internal clocking has stopped. 6. clk frequency equals 100 mhz. 7. this specification applies to components using a clk frequency of 66 mhz or 100 mhz. chapter 15 i/o buffer characteristics 263 21918b/0october 1999 amd-k6 ? - iii processor data sheet 15 i/o buffer characteristics all of the AMD-K6-III processor inputs, outputs, and bidirectional buffers are implemented using a 3.3v buffer design. amd has developed a model that represents the characteristics of the actual i/o buffer to allow system designers to perform analog simulations of AMD-K6-III processor signals that interface with the system logic. analog simulations are used to determine a signals time of flight from source to destination and to ensure that the systems signal quality requirements are met. signal quality measurements include overshoot, undershoot, slope reversal, and ringing. 15.1 i/o buffer model amd provides a model of the AMD-K6-III processor i/o buffer for system designers to use in board-level simulations. this i/o buffer model conforms to the i/o buffer information specification (ibis) . the i/o model contains voltage versus current (v/i) and voltage versus time (v/t) data tables for accurate modeling of i/o buffer behavior. the following list characterizes the properties of the i/o buffer model: n all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. n the pullup, pulldown, power clamp, and ground clamp device v/i tables contain enough data points to accurately represent the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-K6-III processor for those simulators that yield more accurate results based on this wider range. figure 99 and figure 100 on page 264 illustrate the min/typ/max pulldown and pullup v/i curves between 0v and 3.3v. n the rising and falling ramp rates are specified. n the min/typ/max v cc3 operating range is specified as 3.135v, 3.3v, and 3.6v, respectively. n v il = 0.8v, v ih = 2.0v, and v meas = 1.5v 264 i/o buffer characteristics chapter 15 amd-k6 ? - iii processor data sheet 21918b/0october 1999 n the r/l/c of the package is modeled. n the capacitance of the silicon die is modeled. n the model assumes a test load resistance of 50 w . figure 99. pulldown v/i curves figure 100. pullup v/i curves 15.2 i/o model application note for the AMD-K6-III processor i/o buffer ibis model and their application, refer to the amd-k6 ? processor i/o model (ibis) application note , order# 21084. 0 10 20 30 40 50 60 70 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v output (v) i ol (ma) -70 -60 -50 -40 -30 -20 -10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 v output (v) i oh (ma) chapter 15 i/o buffer characteristics 265 21918b/0october 1999 amd-k6 ? - iii processor data sheet 15.3 i/o buffer ac and dc characteristics see signal switching characteristics on page 267 for the AMD-K6-III processor ac timing specifications. see electrical data on page 259 for the AMD-K6-III processor dc specifications. 266 i/o buffer characteristics chapter 15 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 267 16 signal switching characteristics the AMD-K6-III processor signal switching characteristics are presented in table 54 through table 63. valid delay, float, setup, and hold timing specifications are listed. these specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. table 54 and table 55 contain the switching characteristics of the clk input. table 56 through table 59 contain the timings for the normal operation signals. table 60 and table 61 contain the timings for reset and the configuration signals. table 62 and table 63 contain the timings for the test operation signals. all signal timings provided are: n measured between clk, tck, or reset at 1.5 v and the corresponding signal at 1.5 vthis applies to input and output signals that are switching from low to high, or from high to low n based on input signals applied at a slew rate of 1 v/ns between 0 v and 3 v (rising) and 3 v to 0 v (falling) n valid within the operating ranges given in operating ranges on page 259 n based on a load capacitance (c l ) of 0 pf 16.1 clk switching characteristics table 54 and table 55 contain the switching characteristics of the clk input to the AMD-K6-III processor for 100-mhz and 66-mhz bus operation, respectively, as measured at the voltage levels indicated by figure 101 on page 269. the clk period stability specifies the variance (jitter) allowed between successive periods of the clk input measured at 1.5 v. this parameter must be considered as one of the elements of clock skew between the AMD-K6-III processor and the system logic. 268 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.2 clock switching characteristics for 100-mhz bus operation 16.3 clock switching characteristics for 66-mhz bus operation table 54. clk switching characteristics for 100-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 100 mhz in normal mode t 1 clk period 10.0 ns 101 in normal mode t 2 clk high time 3.0 ns 101 t 3 clk low time 3.0 ns 101 t 4 clk fall time 0.15 ns 1.5 ns 101 t 5 clk rise time 0.15 ns 1.5 ns 101 clk period stability 250 ps note note: jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. table 55. clk switching characteristics for 66-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 66.6 mhz in normal mode t 1 clk period 15.0 ns 30.0 ns 101 in normal mode t 2 clk high time 4.0 ns 101 t 3 clk low time 4.0 ns 101 t 4 clk fall time 0.15 ns 1.5 ns 101 t 5 clk rise time 0.15 ns 1.5 ns 101 clk period stability 250 ps note note: jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 269 figure 101. clk waveform 16.4 valid delay, float, setup, and hold timings valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of clk. during boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of tck. the maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. likewise, the minimum valid delay timings are used to analyze hold times to the system logic. the setup and hold time requirements for the AMD-K6-III processor input signals must be met by the system logic to assure the proper operation of the AMD-K6-III processor. the setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of clk and tck, respectively. t 5 2.0 v 1.5 v 0.8 v t 2 t 3 t 4 t 1 270 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.5 output delay timings for 100-mhz bus operation table 56. output delay timings for 100-mhz bus operation symbol parameter description preliminary data figure comments min max t 6 a[31:3] valid delay 1.1 ns 4.0 ns 103 t 7 a[31:3] float delay 7.0 ns 104 t 8 ads# valid delay 1.0 ns 4.0 ns 103 t 9 ads# float delay 7.0 ns 104 t 10 adsc# valid delay 1.0 ns 4.0 ns 103 t 11 adsc# float delay 7.0 ns 104 t 12 ap valid delay 1.0 ns 5.5 ns 103 t 13 ap float delay 7.0 ns 104 t 14 apchk# valid delay 1.0 ns 4.5 ns 103 t 15 be[7:0]# valid delay 1.0 ns 4.0 ns 103 t 16 be[7:0]# float delay 7.0 ns 104 t 17 breq valid delay 1.0 ns 4.0 ns 103 t 18 cache# valid delay 1.0 ns 4.0 ns 103 t 19 cache# float delay 7.0 ns 104 t 20 d/c# valid delay 1.0 ns 4.0 ns 103 t 21 d/c# float delay 7.0 ns 104 t 22 d[63:0] write data valid delay 1.3 ns 4.5 ns 103 t 23 d[63:0] write data float delay 7.0 ns 104 t 24 dp[7:0] write data valid delay 1.3 ns 4.5 ns 103 t 25 dp[7:0] write data float delay 7.0 ns 104 t 26 ferr# valid delay 1.0 ns 4.5 ns 103 t 27 hit# valid delay 1.0 ns 4.0 ns 103 t 28 hitm# valid delay 1.1 ns 4.0 ns 103 t 29 hlda valid delay 1.0 ns 4.0 ns 103 t 30 lock# valid delay 1.1 ns 4.0 ns 103 t 31 lock# float delay 7.0 ns 104 t 32 m/io# valid delay 1.0 ns 4.0 ns 103 t 33 m/io# float delay 7.0 ns 104 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 271 t 34 pcd valid delay 1.0 ns 4.0 ns 103 t 35 pcd float delay 7.0 ns 104 t 36 pchk# valid delay 1.0 ns 4.5 ns 103 t 37 pwt valid delay 1.0 ns 4.0 ns 103 t 38 pwt float delay 7.0 ns 104 t 39 scyc valid delay 1.0 ns 4.0 ns 103 t 40 scyc float delay 7.0 ns 104 t 41 smiact# valid delay 1.0 ns 4.0 ns 103 t 42 w/r# valid delay 1.0 ns 4.0 ns 103 t 43 w/r# float delay 7.0 ns 104 table 56. output delay timings for 100-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max 272 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.6 input setup and hold timings for 100-mhz bus operation table 57. input setup and hold timings for 100-mhz bus operation symbol parameter description preliminary data figure comments min max t 44 a[31:5] setup time 3.0 ns 105 t 45 a[31:5] hold time 1.0 ns 105 t 46 a20m# setup time 3.0 ns 105 note 1 t 47 a20m# hold time 1.0 ns 105 note 1 t 48 ahold setup time 3.5 ns 105 t 49 ahold hold time 1.0 ns 105 t 50 ap setup time 1.7 ns 105 t 51 ap hold time 1.0 ns 105 t 52 boff# setup time 3.5 ns 105 t 53 boff# hold time 1.0 ns 105 t 54 brdy# setup time 3.0 ns 105 t 55 brdy# hold time 1.0 ns 105 t 56 brdyc# setup time 3.0 ns 105 t 57 br dyc# hold time 1.0 ns 105 t 58 d[63:0] read data setup time 1.7 ns 105 t 59 d[63:0] read data hold time 1.5 ns 105 t 60 dp[7:0] read data setup time 1.7 ns 105 t 61 dp[7:0] read data hold time 1.5 ns 105 t 62 eads# setup time 3.0 ns 105 t 63 eads# hold time 1.0 ns 105 t 64 ewbe# setup time 1.7 ns 105 t 65 ewbe# hold time 1.0 ns 105 t 66 flush# setup time 1.7 ns 105 note 2 t 67 flush# hold time 1.0 ns 105 note 2 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 273 t 68 hold setup time 1.7 ns 105 t 69 hold hold time 1.5 ns 105 t 70 ignne# setup time 1.7 ns 105 note 1 t 71 ignne# hold time 1.0 ns 105 note 1 t 72 init setup time 1.7 ns 105 note 2 t 73 init hold time 1.0 ns 105 note 2 t 74 intr setup time 1.7 ns 105 note 1 t 75 intr hold time 1.0 ns 105 note 1 t 76 inv setup time 1.7 ns 105 t 77 inv hold time 1.0 ns 105 t 78 ken# setup time 3.0 ns 105 t 79 ken# hold time 1.0 ns 105 t 80 na# setup time 1.7 ns 105 t 81 na# hold time 1.0 ns 105 t 82 nmi setup time 1.7 ns 105 note 2 t 83 nmi hold time 1.0 ns 105 note 2 t 84 smi# setup time 1.7 ns 105 note 2 t 85 smi# hold time 1.0 ns 105 note 2 t 86 stpclk# setup time 1.7 ns 105 note 1 t 87 stpclk# hold time 1.0 ns 105 note 1 t 88 wb/wt# setup time 1.7 ns 105 t 89 wb/wt# hold time 1.0 ns 105 table 57. input setup and hold timings for 100-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 274 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.7 output delay timings for 66-mhz bus operation table 58. output delay timings for 66-mhz bus operation symbol parameter description preliminary data figure comments min max t 6 a[31:3] valid delay 1.1 ns 6.3 ns 103 t 7 a[31:3] float delay 10.0 ns 104 t 8 ads# valid delay 1.0 ns 6.0 ns 103 t 9 ads# float delay 10.0 ns 104 t 10 adsc# valid delay 1.0 ns 7.0 ns 103 t 11 adsc# float delay 10.0 ns 104 t 12 ap valid delay 1.0 ns 8.5 ns 103 t 13 ap float delay 10.0 ns 104 t 14 apchk# valid delay 1.0 ns 8.3 ns 103 t 15 be[7:0]# valid delay 1.0 ns 7.0 ns 103 t 16 be[7:0]# float delay 10.0 ns 104 t 17 breq valid delay 1.0 ns 8.0 ns 103 t 18 cache# valid delay 1.0 ns 7.0 ns 103 t 19 cache# float delay 10.0 ns 104 t 20 d/c# valid delay 1.0 ns 7.0 ns 103 t 21 d/c# float delay 10.0 ns 104 t 22 d[63:0] write data valid delay 1.3 ns 7.5 ns 103 t 23 d[63:0] write data float delay 10.0 ns 104 t 24 dp[7:0] write data valid delay 1.3 ns 7.5 ns 103 t 25 dp[7:0] write data float delay 10.0 ns 104 t 26 ferr# valid delay 1.0 ns 8.3 ns 103 t 27 hit# valid delay 1.0 ns 6.8 ns 103 t 28 hitm# valid delay 1.1 ns 6.0 ns 103 t 29 hlda valid delay 1.0 ns 6.8 ns 103 t 30 lock# valid delay 1.1 ns 7.0 ns 103 t 31 lock# float delay 10.0 ns 104 t 32 m/io# valid delay 1.0 ns 5.9 ns 103 t 33 m/io# float delay 10.0 ns 104 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 275 t 34 pcd valid delay 1.0 ns 7.0 ns 103 t 35 pcd float delay 10.0 ns 104 t 36 pchk# valid delay 1.0 ns 7.0 ns 103 t 37 pwt valid delay 1.0 ns 7.0 ns 103 t 38 pwt float delay 10.0 ns 104 t 39 scyc valid delay 1.0 ns 7.0 ns 103 t 40 scyc float delay 10.0 ns 104 t 41 smiact# valid delay 1.0 ns 7.3 ns 103 t 42 w/r# valid delay 1.0 ns 7.0 ns 103 t 43 w/r# float delay 10.0 ns 104 table 58. output delay timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max 276 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.8 input setup and hold timings for 66-mhz bus operation table 59. input setup and hold timings for 66-mhz bus operation symbol parameter description preliminary data figure comments min max t 44 a[31:5] setup time 6.0 ns 105 t 45 a[31:5] hold time 1.0 ns 105 t 46 a20m# setup time 5.0 ns 105 note 1 t 47 a20m# hold time 1.0 ns 105 note 1 t 48 ahold setup time 5.5 ns 105 t 49 ahold hold time 1.0 ns 105 t 50 ap setup time 5.0 ns 105 t 51 ap hold time 1.0 ns 105 t 52 boff# setup time 5.5 ns 105 t 53 boff# hold time 1.0 ns 105 t 54 brdy# setup time 5.0 ns 105 t 55 brdy# hold time 1.0 ns 105 t 56 brdyc# setup time 5.0 ns 105 t 57 br dyc# hold time 1.0 ns 105 t 58 d[63:0] read data setup time 2.8 ns 105 t 59 d[63:0] read data hold time 1.5 ns 105 t 60 dp[7:0] read data setup time 2.8 ns 105 t 61 dp[7:0] read data hold time 1.5 ns 105 t 62 eads# setup time 5.0 ns 105 t 63 eads# hold time 1.0 ns 105 t 64 ewbe# setup time 5.0 ns 105 t 65 ewbe# hold time 1.0 ns 105 t 66 flush# setup time 5.0 ns 105 note 2 t 67 flush# hold time 1.0 ns 105 note 2 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 277 t 68 hold setup time 5.0 ns 105 t 69 hold hold time 1.5 ns 105 t 70 ignne# setup time 5.0 ns 105 note 1 t 71 ignne# hold time 1.0 ns 105 note 1 t 72 init setup time 5.0 ns 105 note 2 t 73 init hold time 1.0 ns 105 note 2 t 74 intr setup time 5.0 ns 105 note 1 t 75 intr hold time 1.0 ns 105 note 1 t 76 inv setup time 5.0 ns 105 t 77 inv hold time 1.0 ns 105 t 78 ken# setup time 5.0 ns 105 t 79 ken# hold time 1.0 ns 105 t 80 na# setup time 4.5 ns 105 t 81 na# hold time 1.0 ns 105 t 82 nmi setup time 5.0 ns 105 note 2 t 83 nmi hold time 1.0 ns 105 note 2 t 84 smi# setup time 5.0 ns 105 note 2 t 85 smi# hold time 1.0 ns 105 note 2 t 86 stpclk# setup time 5.0 ns 105 note 1 t 87 stpclk# hold time 1.0 ns 105 note 1 t 88 wb/wt# setup time 4.5 ns 105 t 89 wb/wt# hold time 1.0 ns 105 table 59. input setup and hold timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure comments min max notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 278 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 16.9 reset and test signal timing table 60. reset and configuration signals for 100-mhz bus operation symbol parameter description preliminary data figure comments min max t 90 reset setup time 1.7 ns 106 t 91 r eset hold time 1.0 ns 106 t 92 reset pulse width, v cc and clk stable 15 clocks 106 t 93 reset active after v cc and clk stable 1.0 ms 106 t 94 bf[2:0] setup time 1.0 ms 106 note 3 t 95 bf[2:0] hold time 2 clocks 106 note 3 t 96 intentionally left blank t 97 intentionally left blank t 98 intentionally left blank t 99 flush# setup time 1.7 ns 106 note 1 t 100 flush# hold time 1.0 ns 106 note 1 t 101 flush# setup time 2 clocks 106 note 2 t 102 flush# hold time 2 clocks 106 note 2 notes: 1. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which reset is sampled negated. 2. if asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of reset. 3. bf[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 279 table 61. reset and configuration signals for 66-mhz bus operation symbol parameter description preliminary data figure comments min max t 90 reset setup time 5.0 ns 106 t 91 r eset hold time 1.0 ns 106 t 92 reset pulse width, v cc and clk stable 15 clocks 106 t 93 reset active after v cc and clk stable 1.0 ms 106 t 94 bf[2:0] setup time 1.0 ms 106 note 3 t 95 bf[2:0] hold time 2 clocks 106 note 3 t 96 intentionally left blank t 97 intentionally left blank t 98 intentionally left blank t 99 flush# setup time 5.0 ns 106 note 1 t 100 flush# hold time 1.0 ns 106 note 1 t 101 flush# setup time 2 clocks 106 note 2 t 102 flush# hold time 2 clocks 106 note 2 notes: 1. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which reset is sampled negated. 2. if asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of reset. 3. bf[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. 280 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 table 62. tck waveform and trst# timing at 25 mhz symbol parameter description preliminary data figure comments min max tck frequency 25 mhz 107 t 103 tck period 40.0 ns 107 t 104 tck high time 14.0 ns 107 t 105 tck low time 14.0 ns 107 t 106 tck fall time 5.0 ns 107 note 1, 2 t 107 tck rise time 5.0 ns 107 note 1, 2 t 108 trst# pulse width 30.0 ns 108 asynchronous notes: 1. rise/fall times can be increased by 1.0 ns for each 10 mhz that tck is run below its maximum frequency of 25 mhz. 2. rise/fall times are measured between 0.8 v and 2.0 v. table 63. test signal timing at 25 mhz symbol parameter description preliminary data figure notes min max t 109 tdi setup time 5.0 ns 109 note 2 t 110 tdi hold time 9.0 ns 109 note 2 t 111 tms setup time 5.0 ns 109 note 2 t 112 tms hold time 9.0 ns 109 note 2 t 113 tdo valid delay 3.0 ns 13.0 ns 109 note 1 t 114 tdo float delay 16.0 ns 109 note 1 t 115 all outputs (non-test) valid delay 3.0 ns 13.0 ns 109 note 1 t 116 all outputs (non-test) float delay 16.0 ns 109 note 1 t 117 all inputs (non-test) setup time 5.0 ns 109 note 2 t 118 all inputs (non-test) hold time 9.0 ns 109 note 2 notes: 1. parameter is measured from the tck falling edge. 2. parameter is measured from the tck rising edge. 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 281 figure 102. diagrams key figure 103. output valid delay timing must be steady can change from high to low can change from low to high (does not apply) dont care, any change permitted steady changing from high to low changing from low to high changing, state unknown center line is high impedance state waveform inputs outputs min max valid n +1 t v valid n clk output signal t x t x 1.5 v v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42 282 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 104. maximum float delay timing figure 105. input setup and hold timing t x t x t x valid t x t v min output signal t f clk 1.5 v v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42 f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43 clk t x t x t x t x input signal t s t h 1.5 v s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88 h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 16 signal switching characteristics 283 figure 106. reset and configuration timing t x clk reset t x t 90 flush# (synchronous) 1.5 v 1.5 v 1.5 v ? ? ? t 92, 93 t 91 t 99 t 100 ? ? ? bf[2:0] (asynchronous) t 94 ? ? ? t 95 flush# (asynchronous) t 101 t 102 ? ? ? ? ? ? 284 signal switching characteristics chapter 16 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 107. tck waveform figure 108. trst# timing figure 109. test signal timing diagram t 107 2.0 v 1.5 v 0.8 v t 10 5 t 10 6 t 103 t 10 4 1.5 v t 10 8 tck tdi, tms tdo output signals input signals t 10 3 t 10 9, 111 t 110, 112 t 113 t 115 t 116 t 117 t 118 t 114 1.5 v 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 17 thermal design 285 17 thermal design 17.1 package thermal specifications the AMD-K6-III processor operating specification calls for the case temperature (t c ) to be in the range of 0c to 65c. the ambient temperature (t a ) is not specified as long as the case temperature is not violated. the case temperature must be measured on the top center of the package. table 64 shows the AMD-K6-III processor thermal specifications. figure 110 on page 286 shows the thermal model of a processor with a passive thermal solution. the case-to-ambient temperature (t ca ) can be calculated from the following equation: t ca = p max ? q ca = p max ? ( q if + q sa ) where: p max = maximum power consumption q ca = case-to-ambient thermal resistance q if = interface material thermal resistance q sa = sink-to-ambient thermal resistance table 64. package thermal specification q jc junction-case maximum thermal power 2.2 v component 2.4 v component 400 mhz 450 mhz 400 mhz 450 mhz 1.0 c/w 18.10 w 20.20 w 26.80 w 29.50 w stop grant mode 4.40 w 4.44 w 5.30 w 5.34 w stop clock mode 4.00 w 4.00 w 4.80 w 4.80 w t c case temperature 0cC70c 0cC65c 286 thermal design chapter 17 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 110. thermal model figure 111 illustrates the case-to-ambient temperature (t ca ) in relation to the power consumption (x-axis) and the thermal resistance (y-axis). if the power consumption and case temperature are known, the thermal resistance ( q ca ) requirement can be calculated for a given ambient temperature (t a ) value. figure 111. power consumption versus thermal resistance temperature thermal q sa q ca q if (c/w) (ambient) case sink t ca resistance 0.0 0.5 1.0 1.5 2.0 2.5 3.0 10 w12 w14 w16 w18 w20 w22 w24 w26 w28 w30 w32 w power consumption (watts) thermal resistance (deg c/w) 30 deg c 25 deg c 20 deg c 15 deg c t ca = t c - t a 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 17 thermal design 287 the thermal resistance of a heatsink is determined by the heat dissipation surface area, the material and shape of the heatsink, and the airflow volume across the heatsink. in general, the larger the surface area the lower the thermal resistance. the required thermal resistance of a heatsink ( q sa ) can be calculated using the following example: if: t c = 65c t a = 45c p max = 29.50w then: thermal grease is recommended as interface material because it provides the lowest thermal resistance ( @ 0.20c/w). the required thermal resistance ( q sa ) of the heatsink in this example is calculated as follows: q sa = q ca C q if = 0.678 C 0.20 = 0.478(c/w) heat dissipation path figure 112 illustrates the heat dissipation path of the processor. due to the lower thermal resistance between the processor die junction and case, most of the heat generated by the processor is transferred from the top surface of the case. the small amount of heat generated from the bottom side of the processor where the processor socket blocks the convection can be safely ignored. figure 112. processor heat dissipation path q ca t c t a C p max ------------------ - ? ?? 20 c 29.5w ----------------- - 0.678 cw == thin lid case temperature ambient temperature 288 thermal design chapter 17 amd-k6 ? - iii processor data sheet 21918b/0october 1999 measuring case temperature the processor case temperature is measured to ensure that the thermal solution meets the processors operational specification. this temperature should be measured on the top center of the package, where most of the heat is dissipated. figure 113 shows the correct location for measuring the case temperature. the tip of the thermocouple should be secured to the package surface with a small amount of thermally conductive epoxy. it is also recommended to secure a second location along the thermocouple to avoid any movement during testing. if a heatsink is installed while measuring, the thermocouple must be installed into the heatsink via a small hole drilled through the heatsink base (for example, 1/16 of an inch). secure the thermocouple to the base of the heatsink by filling the small hole with thermal epoxy, allowing the tip of the thermocouple to protrude the epoxy and touch the top of the processor case. figure 113. measuring case temperature 17.2 layout and airflow considerations voltage regulator a voltage regulator is required to support the lower voltage (3.3 v and lower) to the processor. in most applications, the voltage regulator is designed with power transistors. as a result, additional heatsinks are required to dissipate the heat from the power transistors. figure 114 shows the voltage regulator placed parallel to the processor with the airflow aligned with the devices. with this alignment, the heat generated by the voltage regulator has minimal effect on the processor. thermocouple thermally conductive epoxy 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 17 thermal design 289 figure 114. voltage regulator placement a heatsink and fan combination can deliver much better thermal performance than a heatsink alone. more importantly, with a fan/sink the airflow requirements in a system design are not as critical. a unidirectional heatsink with a fan moves air from the top of the heatsink to the side. in this case, the best location for the voltage regulator is on the side of the processor in the path of the airflow exiting the fan sink (see figure 115). this location guarantees that the heatsinks on both the processor and the regulator receive adequate air circulation. figure 115. airflow for a heatsink with fan processor airflow voltage regulator airflow ideal areas for voltage regulator 290 thermal design chapter 17 amd-k6 ? - iii processor data sheet 21918b/0october 1999 airflow management in a system design complete airflow management in a system is important. in addition to the volume of air, the path of the air is also important. figure 116 shows the airflow in a dual-fan system. the fan in the front end pulls cool air into the system through intake slots in the chassis. the power supply fan forces the hot air out of the chassis. the thermal performance of the heatsink can be maximized if it is located in the shaded area, where it receives greatest benefit from this air exchange system. figure 116. airflow path in a dual-fan system drive bays p/s vents v e n t s fan fan main board front 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 17 thermal design 291 figure 117 shows the airflow management in a system using the atx form-factor. the orientation of the power supply fan and the motherboard are modified in the atx platform design. the power supply fan pulls cool air through the chassis and across the processor. the processor is located near the power supply fan, where it can receive adequate airflow without an auxiliary fan. the arrangement significantly improves the airflow across the processor with minimum installation cost. figure 117. airflow path in an atx form-factor system for more information about thermal design considerations, see the amd-k6 ? processor thermal solution design application note , order# 21085. p/s main board drive bays f a n 292 thermal design chapter 17 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 18 pin description diagram 293 18 pin description diagram figure 118. amd-k6 ? - iii processor top-side view 294 pin description diagram chapter 18 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 119. amd-k6 ? - iii processor pin-side view 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 19 pin designations 295 19 pin designations amd-k6 ? - iii processor functional grouping address data control test nc v cc2 v cc3 v ss pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin no. pin no. pin no. pin no. a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 al-35 am-34 ak-32 an-33 al-33 am-32 ak-30 an-31 al-31 al-29 ak-28 al-27 ak-26 al-25 ak-24 al-23 ak-22 al-21 af-34 ah-36 ae-33 ag-35 aj-35 ah-34 ag-33 ak-36 ak-34 am-36 aj-33 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 k-34 g-35 j-35 g-33 f-36 f-34 e-35 e-33 d-34 c-37 c-35 b-36 d-32 b-34 c-33 a-35 b-32 c-31 a-33 d-28 b-30 c-29 a-31 d-26 c-27 c-23 d-24 c-21 d-22 c-19 d-20 c-17 c-15 d-16 c-13 d-14 c-11 d-12 c-09 d-10 d-08 a-05 e-09 b-04 d-06 c-05 e-07 c-03 d-04 e-05 d-02 f-04 e-03 g-05 e-01 g-03 h-04 j-03 j-05 k-04 l-05 l-03 m-04 n-03 a20m# ads# adsc# ahold apchk# be0# be1# be2# be3# be4# be5# be6# be7# bf0 bf1 bf2 boff# brdy# brdyc# breq cache# clk d/c# eads# ewbe# ferr# flush# hit# hitm# hlda hold ignne# init intr inv ken# lock# m/io# na# nmi pcd pchk# pwt reset scyc smi# smiact# stpclk# vcc2det vcc2h/l# w/r# wb/wt# ak-08 aj-05 am-02 v-04 ae-05 al-09 ak-10 al-11 ak-12 al-13 ak-14 al-15 ak-16 y-33 x-34 w-35 z-04 x-04 y-03 aj-01 u-03 ak-18 ak-04 am-04 w-03 q-05 an-07 ak-06 al-05 aj-03 ab-04 aa-35 aa-33 ad-34 u-05 w-05 ah-04 t-04 y-05 ac-33 ag-05 af-04 al-03 ak-20 al-17 ab-34 ag-03 v-34 al-01 an-05 am-06 aa-05 tck m-34 tdi n-35 tdo n-33 tms p-34 trst# q-33 parity ap ak-02 dp0 d-36 dp1 d-30 dp2 c-25 dp3 d-18 dp4 c-07 dp5 f-06 dp6 f-02 dp7 n-05 a-37 e-17 e-25 r-34 s-33 s-35 w-33 aj-15 aj-23 al-19 an-35 inc c-01 h-34 y-35 z-34 ac-35 al-07 an-01 an-03 rsvd j-33 l-35 p-04 q-03 q-35 r-04 s-03 s-05 aa-03 ac-03 ac-05 ad-04 ae-03 ae-35 key ah-32 a-07 a-09 a-11 a-13 a-15 a-17 b-02 e-15 g-01 j-01 l-01 n-01 q-01 s-01 u-01 w-01 y-01 aa-01 ac-01 ae-01 ag-01 aj-11 an-09 an-11 an-13 an-15 an-17 an-19 a-19 a-21 a-23 a-25 a-27 a-29 e-21 e-27 e-37 g-37 j-37 l-33 l-37 n-37 q-37 s-37 t-34 u-33 u-37 w-37 y-37 aa-37 ac-37 ae-37 ag-37 aj-19 aj-29 an-21 an-23 an-25 an-27 an-29 a-03 am-20 b-06 am-22 b-08 am-24 b-10 am-26 b-12 am-28 b-14 am-30 b-16 an-37 b-18 b-20 b-22 b-24 b-26 b-28 e-11 e-13 e-19 e-23 e-29 e-31 h-02 h-36 k-02 k-36 m-02 m-36 p-02 p-36 r-02 r-36 t-02 t-36 u-35 v-02 v-36 x-02 x-36 z-02 z-36 ab-02 ab-36 ad-02 ad-36 af-02 af-36 ah-02 aj-07 aj-09 aj-13 aj-17 aj-21 aj-25 aj-27 aj-31 aj-37 al-37 am-08 am-10 am-12 am-14 am-16 am-18 296 pin designations chapter 19 amd-k6 ? - iii processor data sheet 21918b/0october 1999 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 20 package specifications 297 20 package specifications 20.1 321-pin staggered cpga package specification table 65. 321-pin staggered cpga package specification symbol millimeters inches min max notes min max notes a 49.28 49.78 1.940 1.960 b 45.59 45.85 1.795 1.805 c 31.01 32.89 1.221 1.295 d 44.90 45.10 1.768 1.776 e 2.91 3.63 0.115 0.143 f 1.30 1.52 0.051 0.060 g 3.05 3.30 0.120 0.130 h 0.43 0.51 0.017 0.020 m 2.29 2.79 0.090 0.110 n 1.14 1.40 0.045 0.055 d 1.52 2.29 0.060 0.090 e 1.52 2.54 0.060 0.100 f 0.13 flatness 0.005 flatness 298 package specifications chapter 20 amd-k6 ? - iii processor data sheet 21918b/0october 1999 figure 120. 321-pin staggered cpga package specification 21918b/0october 1999 amd-k6 ? - iii processor data sheet chapter 21 ordering information 299 21 ordering information standard amd-k6 ? - iii processor model 9 products amd standard products are available in several operating ranges. the ordering part number (opn) is formed by a combination of the elements below. a amd-k6- iii package type family/core a = 321-pin cpga amd-k6- iii case temperature r= 0cC70c x= 0cC65c /450 performance rating /450 /400 operating voltage f = 2.1 v C 2.3 v (core) / 3.135 v C 3.6 v (i/o) h = 2.3 v C 2.5 v (core) / 3.135 v C 3.6 v (i/o) f x table 66. valid ordering part number combinations opn package type operating voltage case temperature amd-k6- iii /450afx 321-pin cpga 2.1vC2.3v (core) 3.135vC3.6v (i/o) 0cC65c amd-k6- iii /450ahx 321-pin cpga 2.3vC2.5v (core) 3.135vC3.6v (i/o) 0cC65c amd-k6- iii /400afr 321-pin cpga 2.1vC2.3v (core) 3.135vC3.6v (i/o) 0cC70c amd-k6- iii /400ahx 321-pin cpga 2.3vC2.5v (core) 3.135vC3.6v (i/o) 0cC65c note: this table lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly-released combinations. 300 ordering information chapter 21 amd-k6 ? - iii processor data sheet 21918b/0october 1999 index 301 21918b/0october 1999 amd-k6 ? - iii processor data sheet index numerics 100-mhz bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 272 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 321-pin staggered cpga package . . . . . . . . . . . . . . . . . . . . . 1 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 3dnow!. . . . . . .1 C 3 , 7 , 10 , 13 C 17 , 21 , 54 , 116 , 173 , 177 , 194 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C 17 instruction compatibility, floating-point and . . . . . . . . . 211 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 , 212 register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 9 66-mhz bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 276 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 a a[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 , 214 a20m# masking of cache accesses . . . . . . . . . . . . . . . . . . 202 absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 accelerated graphic port (agp) . . . . . . . . . . . . . . . . . . . . . 1 , 3 acknowledge, interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 address bus . . . . . . . . . . . . . . . 86 C 91 , 100 , 127 , 148 , 152 , 154 , 197 hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 stack, return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 adsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 ahold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 , 250 -initiated inquire hit to modified line. . . . . . . . . . . . . . . 152 -initiated inquire hit to shared or exclusive line . . . . . . 150 -initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 airflow consideration, layout and . . . . . . . . . . . . . . . . . . . . . . . . . 288 management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 allocate, write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 apchk#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 C 19 asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 b backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 base address, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 be[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 , 173 , 253 bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 bits, predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 182 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 boff# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 , 156 locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 boundary scan register (bsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 branch execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 C 2 , 9 , 19 prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 C 18 target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 brdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 breq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 bsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 buffer characteristics, i/o . . . . . . . . . . . . . . . . . . . . . . . . . 263 buffer model, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 built-in self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 reads, pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 ready copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 , 174 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 bus 100-mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 address . . . . . . . . . . . . 88 C 91 , 100 , 127 , 148 , 152 , 154 , 197 arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 142 backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 cycles, special. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 data . 88 , 91 , 94 , 98 C 99 , 114 , 117 , 130 C 132 , 148 , 154 , 158 enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 hold request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 129 bus states address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 data-na# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 bypass instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 c cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 flush. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 302 index amd-k6 ? - iii processor data sheet 21918b/0october 1999 l1 . . . 1 , 9 C 10 , 38 , 138 , 142 , 148 , 152 , 164 , 179 , 188 C 189 , 192 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 , 202 , 223 l2 . . .1 , 3 , 9 C 10 , 39 , 42 C 43 , 138 , 142 , 148 , 152 , 164 , 179 , 188 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 C 240 l3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 235 C 236 mesi states in the data . . . . . . . . . . . . . . . . . . . . . . . . . . 181 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 , 203 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 trilevel design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 9 cache# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 , 184 cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 page, write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 C 187 , 237 replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 , 199 capture-dr state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 capture-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ceramic pin grid array (cpga) . . . . . . . . . . . . . . . . .1 C 2 , 297 characteristics i/o buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 i/o buffer ac and dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 clock states halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 , 252 C 253 stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 , 251 stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 coherency states, writethrough vs. writeback. . . . . . . . . 202 coherency, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 compatibility, floating-point, mmx, and 3dnow! instruc- tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 configuration and initialization, power-on . . . . . . . . . . . . 173 connection requirements, pin . . . . . . . . . . . . . . . . . . . . . . 257 connections, power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 unit, scheduler/instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 8 counter, time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 cpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 C 2 , 297 cycle hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 142 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 cycles bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 inquire85 C 90 , 100 , 104 C 105 , 118 , 123 , 138 , 142 , 144 , 146 , 148 , 150 C 152 , 154 , 156 , 160 , 197 , 202 , 235 , 249 C 252 inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 142 interrupt acknowledge . . . . . . . . . . 86 , 89 , 91 , 97 , 112 , 122 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 87 pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 writeback . . 85 , 87 C 88 , 101 , 104 , 123 , 138 , 146 , 150 , 152 , 154 , . . . . . . . . . . . . . . . . . . . . . 156 , 160 , 184 , 236 , 252 d d/c#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 d[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 data bus . . 88 , 91 , 94 , 98 C 99 , 114 , 117 , 130 C 132 , 148 , 154 , 158 cache, mesi states in the . . . . . . . . . . . . . . . . . . . . . . . . 181 parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 data types 3dnow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 mmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 data/code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 241 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 decode, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 decoupling recommendations. . . . . . . . . . . . . . . . . . . . . . 256 descriptions, signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 design, thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 designations, pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 device identification register . . . . . . . . . . . . . . . . . . . . . . 230 diagram, pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 293 diagrams, timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 disabling, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dissipation, power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 dp[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 drive strength, selectable . . . . . . . . . . . . . . . . . . . . . . . . . 263 driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 e eads#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 efer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 176 , 203 eflags register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 environment, software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ewbe control (ewbec) . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 203 , 250 exception . . . . 89 C 90 , 99 , 102 , 114 , 166 , 211 , 222 , 245 C 247 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 C 27 floating-point . . . . . . . . . . . . . . . . . . . . . . 102 , 106 , 209 C 211 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 handling floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 209 interrupts, and debug in smm . . . . . . . . . . . . . . . . . . . . 222 mmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 execution unit 3dnow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 16 C 17 branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 14 , 19 index 303 21918b/0october 1999 amd-k6 ? - iii processor data sheet floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . 2 , 7 , 14 , 209 load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 14 multimedia . . . . . . . . . . . . . . . . . . . . . . 2 , 7 , 14 , 16 C 17 , 211 register x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 14 , 16 C 17 register y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 14 , 16 C 17 store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 14 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 6 C 8 , 15 external address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 write buffer empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 f ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 , 210 C 211 fetch, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 , 125 floated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 floating-point and mmx/3dnow! instruction compatibility . . . . . . . . . 211 and multimedia execution units . . . . . . . . . . . . . . . . . . . 209 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 flush# . . . . . . . . . . . . . . . . . . . . . . . . 103 , 173 , 198 , 224 , 250 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 , 268 , 280 operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 , 96 , 173 frequency multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 g gate descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 , 53 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . 22 global ewbe disable (gewbed) . . . . . . . . . . . . . . . . . . . 203 grounding, power and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 h halt state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 handling floating-point exceptions. . . . . . . . . . . . . . . . . . 209 heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 history table, branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 modified line, ahold-initiated inquire . . . . . . . . . . . . 152 modified line, hold-initiated inquire . . . . . . . . . . . . . . 146 shared or exclusive line, ahold-initiated inquire. . . . 150 shared or exclusive line, hold-initiated inquire . . . . . 144 hit# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 hitm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 hlda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 -initiated inquire hit to modified line. . . . . . . . . . . . . . . 146 -initiated inquire hit to shared or exclusive line . . . . . . 144 hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . .105 , 142 C 144 and hold acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . 142 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 , 282 i i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 265 buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 buffer model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . 141 model application note . . . . . . . . . . . . . . . . . . . . . . . . . . 264 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 ibis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 ieee 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 225 ieee 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 25 , 209 ieee 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 , 210 C 211 ignore numeric exception . . . . . . . . . . . . . . . . . . . . . . . . . 106 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 , 250 -initiated transition from protected mode to real mode 170 state of processor after . . . . . . . . . . . . . . . . . . . . . . . . . . 177 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 power-on configuration and . . . . . . . . . . . . . . . . . . . . . . 173 input setup and hold timings for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . 272 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 , 147 , 149 , 249 and bus arbitration cycles. . . . . . . . . . . . . . . . . . . . . . . . 142 cycle hit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . 104 cycles.85 C 90 , 100 , 104 C 105 , 118 , 123 , 138 , 142 , 144 , 146 , 148 , 150 C 152 , 154 , 156 , 160 , 197 , 202 , 235 , 249 C 252 miss, ahold-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . 148 instruction decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3dnow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 , 211 emms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 femms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 mmx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 , 211 prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 194 tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 wbinvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 integer data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 C 19 snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 interrupt . . 108 , 117 , 162 , 166 C 167 , 170 , 177 , 209 C 211 , 214 , 222 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 , 252 acknowledge . . . . . . . . . 86 , 94 , 97 , 108 , 110 , 114 , 158 , 162 acknowledge cycles . . . . . . . . . . . . 86 , 89 , 91 , 97 , 112 , 122 descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . 45 flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 , 117 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 redirection bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 service routine . . . . . . . . . . . . . . . . . . . . . 108 , 112 , 210 , 213 system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 type of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupts 304 index amd-k6 ? - iii processor data sheet 21918b/0october 1999 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 exceptions and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 intr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 irq13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 nmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 intr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 , 250 inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 invalidation request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 invd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 k ken# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 l l1 cache1 , 9 C 10 , 38 , 138 , 142 , 148 , 152 , 164 , 179 , 188 C 189 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 , 197 , 202 l2 cache . 1 , 3 C 4 , 9 C 10 , 39 , 42 C 43 , 103 C 104 , 123 , 126 , 138 , 142 , 148 , 152 , 164 , 179 C 183 , 185 C 189 , 192 , 194 C 195 , . . . . . . . . . . . . . . . . . . . . . 197 C 202 , 223 , 235 , 237 C 240 l2aar . . . . . . . . . . . . . . . . . . . . . . . 37 , 42 , 186 , 223 , 237 C 240 l3 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 3 , 235 C 236 limit, write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 line fills, cache- . . . . . . . . . . . . . . . . . . . . . . . . .186 C 187 , 237 lock# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 locked cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 operation with boff# intervention . . . . . . . . . . . . . . . . 160 operation, basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 logic branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 C 18 external support of floating-point exceptions . . . . . . . . 209 m m/io# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 machine check exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 176 mctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 C 38 , 176 memory or i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 read and write, misaligned single-transfer . . . . . . . . . . 134 read and write, single-transfer . . . . . . . . . . . . . . . . . . . . 132 reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 type range register (mtrr) . . . . . . . . . . . . . . . . . . . 41 , 205 mesi. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 9 , 142 , 146 , 181 , 202 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 181 , 183 states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 181 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 enhanced risc86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 misaligned i/o read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 single-transfer memory read and write . . . . . . . . . . . . . 134 mmx technology . . . . . . . . . . . .13 C 17 , 21 , 54 , 116 , 173 , 177 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 instruction compatibility, floating-point and . . . . . . . . . 211 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 , 212 register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mode, tri-state test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . 37 msr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 mtrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 205 multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C 17 , 211 functional unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 n na# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 negated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 next address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 , 250 no-connect pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 , 257 non-maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 non-pipelined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 o operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 operation, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 organization, cache. . . . . . . . . . . . . . . . . . . . . . . . . . . 179 , 203 output delay timings for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . 270 for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 274 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 p package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 page cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 directory entry (pde) . . . . . . . . . . . . . . . . . . . . . 48 C 49 , 183 table entry (pte) . . . . . . . . . . . . . . . . . . . . . . . . . 48 , 50 , 183 writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 parity. . . . . . . . . . . . . . . . . . . . . . . . . . 84 , 89 , 91 , 99 , 114 , 132 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 , 99 , 114 check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 C 90 , 99 , 114 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 , 114 , 148 , 226 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 , 183 , 192 pchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 pfir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 C 42 , 176 pin connection requirements . . . . . . . . . . . . . . . . . . . . . . . . 257 description diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 130 C 131 , 136 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register x and y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 8 pipelined. . . . . . . . . .9 , 16 , 112 , 131 , 136 C 137 , 154 , 179 , 194 burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 87 , 98 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pointer, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 power index 305 21918b/0october 1999 amd-k6 ? - iii processor data sheet and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 power-on configuration and initialization . . . . . . . . . . . . . 173 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 C 10 , 182 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 194 psor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 176 pwt instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 r ranges, operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 ratings, absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 read and write basic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 misaligned i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 reads, burst reads and pipelined burst . . . . . . . . . . . . . . 136 register boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 bypass (br) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 data types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . 28 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 241 floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 register x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register x and y pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 register y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 , 21 , 174 , 211 3dnow!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 29 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 device identification (dir) . . . . . . . . . . . . . . . . . . . . . . . 230 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 dr6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 dr7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 eflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 mmx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 29 pfir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 psor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 tr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 uwccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 x and y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 C 16 regulator, voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 replacement, cache-line . . . . . . . . . . . . . . . . . . . . . . 188 , 199 requirements, pin connection . . . . . . . . . . . . . . . . . . . . . . 257 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 , 174 , 250 and test signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 278 signals sampled during. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 state of processor after. . . . . . . . . . . . . . . . . . . . . . . . . . . 174 return address stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision identifier, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 risc86 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 , 222 rsvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 s sample/preload instruction . . . . . . . . . . . . . . . . . . . . 232 sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 scheduler centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 instruction control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 scyc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 sector, write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 , 194 segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 50 C 52 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 task state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . 263 shift-dr state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 shift-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 267 terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timing, reset and test. . . . . . . . . . . . . . . . . . . . . . . . . . 278 signals a[31:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a20m# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 , 214 ads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 adsc#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ahold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 , 250 ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 apchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 be[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 bf[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 , 253 boff# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 , 156 brdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 breq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 cache# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 , 184 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 d/c#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 d[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 dp[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 eads#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 203 , 250 ferr#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 211 flush# . . . . . . . . . . . . . . . . . . . . . 103 , 173 , 198 , 224 , 250 hit# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 hitm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 hlda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ignne#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 , 211 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 , 250 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 , 250 inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ken# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 lock#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 m/io#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 na# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 , 250 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 pcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 pchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 pwt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 , 250 rsvd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 306 index amd-k6 ? - iii processor data sheet 21918b/0october 1999 sampled during reset . . . . . . . . . . . . . . . . . . . . . . . . . . 173 scyc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 , 213 , 250 smiact# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 213 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 , 251 tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 tdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 vcc2det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 vcc2h/l# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 w/r#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 wb/wt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 simd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 , 9 single instruction multiple data (simd). . . . . . . . . . . . . . 2 , 9 single-transfer memory read and write. . . . . . . . . . . . . . 132 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 , 213 , 250 smiact# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 213 smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 state-save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 snoop . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 123 , 138 , 198 , 201 snooping internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 special bus cycle . . . . . . . . . . . . . . . . . . 94 , 119 , 164 C 167 , 220 , 251 cycle 101 , 103 , 119 , 126 , 138 , 164 , 166 C 167 , 186 , 250 C 251 specifications package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 package thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 speculative ewbe disable (sewbed) . . . . . . . . . . . . . . . 204 split cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 stack, return address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 state machine diagram, bus . . . . . . . . . . . . . . . . . . . . . . . . 129 state of processor after init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 states, cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 state-save area, smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 , 252 C 253 grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . 249 C 252 grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 , 251 C 252 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 , 251 super7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 , 3 C 4 initiative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 267 100-mhz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 268 66-mhz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 input setup and hold timings for 100-mhz bus . . . . . . . 272 input setup and hold timings for 66-mhz bus . . . . . . . . 276 output delay timings for 100-mhz bus . . . . . . . . . . . . . . 270 output delay timings for 66-mhz bus . . . . . . . . . . . . . . . 274 signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 valid delay, float, setup, and hold timings . . . . . . . . . . . 269 syscall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 syscall/sysret target address register (star) .37 , 40 , 176 sysret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 system design, airflow management in a . . . . . . . . . . . . . . . . . . 290 management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 117 management interrupt active . . . . . . . . . . . . . . . . . . . . . 118 management mode (smm) . . . . . . . . . . . . . . . . . . . . . . . 213 t table, branch history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 tap controller states capture-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 capture-ir. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 shift-dr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 shift-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 update-dr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 update-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 highz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 tap registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . . 226 tap signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 target cache, branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 task state segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 tdi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 , 285 C 286 case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 terminology, signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 test access port, boundary-scan . . . . . . . . . . . . . . . . . . . . . . . 225 and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 -logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 mode select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mode, tri-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 , 286 , 289 C 290 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 layout and airflow consideration . . . . . . . . . . . . . . . . . . 288 measuring case temperature . . . . . . . . . . . . . . . . . . . . . 288 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 285 time stamp counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 timing diagram test signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 127 , 133 C 171 tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 tr12 . . . . . . . . . . . . . . . . . . . . . . . . 37 C 38 , 176 , 184 , 192 , 235 transition from protected mode to real mode, init-initi- ated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 translation lookaside buffer (tlb) . . . . . . . . . . . . . . . . . 179 trap dword, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 trilevel cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 index 307 21918b/0october 1999 amd-k6 ? - iii processor data sheet tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 C 38 , 176 , 250 C 251 tss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 52 C 53 , 217 , 245 u uc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 uncacheable memory. . . . . . . . . . . . . . . . . . . . . . .41 , 204 C 205 uwccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 174 , 176 , 205 v vcc2det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 vcc2h/l# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 voltage . . . . . . . . . . . . . . . . 121 , 128 , 255 , 259 , 261 , 263 , 267 ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 C 289 w w/r#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 wb/wt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 wbinvd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 wc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 whcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 , 40 , 176 , 193 write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 , 194 write allocate . . . . . . . . . . . . . . . . . . . 182 , 189 , 192 C 193 , 195 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 logic mechanisms and conditions . . . . . . . . . . . . . . . . . . 192 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 write/read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 writeback96 , 98 C 99 , 109 , 115 , 118 , 123 , 126 , 138 C 139 , 164 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 , 202 , 254 burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 9 cycles . 85 , 87 C 88 , 101 , 104 , 123 , 138 , 146 , 150 , 152 , 154 , 156 , . . . . . . . . . . . . . . . . . . . . . . . . . 160 , 184 , 236 , 252 or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 write-combining memory . . . . . . . . . . . . . . . . . . .41 , 204 C 205 writethrough vs. writeback coherency states . . . . . . . . . 202 308 index amd-k6 ? - iii processor data sheet 21918b/0october 1999 |
Price & Availability of AMD-K6-III
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